Inventor · disambiguated record
Jane W. Sowards
Also filed as: SOWARDS JANE · SOWARDS JANE W · SOWARDS JANE WANG
11 granted patents·2 pending applications·401 citations·filing 1999–2024
92Inventor score
Top patents by PatentIndex Score
13 records- 0195US6366117B1Nonvolatile/battery-backed key in PLDXILINX INC·Filed 2000·Granted Apr 2, 2002·126 cites·7 claims
- 0294US6441641B1Programmable logic device with partial battery backupXILINX INC·Filed 2000·Granted Aug 27, 2002·113 cites·6 claims
- 0389US6798239B2Programmable gate array having interconnecting logic to support embedded fixed logic circuitryXILINX INC·Filed 2001·Granted Sep 28, 2004·62 cites·17 claims
- 0488US7420392B2Programmable gate array and embedded circuitry initialization and processingXILINX INC·Filed 2004·Granted Sep 2, 2008·35 cites·45 claims
- 0585US7765498B1Methods of incorporating process-induced layout dimension changes into an integrated circuit simulation netlistXILINX INC·Filed 2007·Granted Jul 27, 2010·16 cites·17 claims
- 0678US7932563B2Techniques for improving transistor-to-transistor stress uniformityXILINX INC·Filed 2009·Granted Apr 26, 2011·10 cites·15 claims
- 0778US7793238B1Method and apparatus for improving a circuit layout using a hierarchical layout descriptionXILINX INC·Filed 2008·Granted Sep 7, 2010·10 cites·19 claims
- 0872US9923051B1Substrate noise isolation structures for semiconductor devicesXILINX INC·Filed 2016·Granted Mar 20, 2018·2 cites·20 claims
- 0971US8224637B1Method and apparatus for modeling transistors in an integrated circuit designSOWARDS JANE W·Filed 2007·Granted Jul 17, 2012·9 cites·19 claims
- 1067US11860228B2Integrated circuit chip testing interface with reduced signal wiresXILINX INC·Filed 2022·Granted Jan 2, 2024·0 cites·20 claims
- 1164US6218864B1Structure and method for generating a clock enable signal in a PLDXILINX INC·Filed 1999·Granted Apr 17, 2001·18 cites·22 claims
- 1262US2025149390A1Wafer process for probing bump placement on multiple small power pads without displacing surrounding signal padsXILINX INC·Filed 2024·Application pending·0 cites
- 1358US2025185311A1Substrate noise isolation structures for electronic devicesXILINX INC·Filed 2023·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →