Inventor · disambiguated record
Massoud Pedram
Also filed as: PEDRAM MASSOUD
12 granted patents·3 pending applications·67 citations·filing 2002–2022
89Inventor score
Top patents by PatentIndex Score
15 records- 0185US7400175B2Recycling charge to reduce energy consumption during mode transition in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuitsFUJITSU LTD·Filed 2007·Granted Jul 15, 2008·16 cites·18 claims
- 0282US7573775B2Setting threshold voltages of cells in a memory block to reduce leakage in the memory blockFUJITSU LTD·Filed 2007·Granted Aug 11, 2009·15 cites·14 claims
- 0379US10707873B2Superconducting magnetic field programmable gate arrayUNIV SOUTHERN CALIFORNIA·Filed 2019·Granted Jul 7, 2020·3 cites·33 claims
- 0468US8094118B2Dynamic backlight scaling for power minimization in a backlit TFT-LCDPEDRAM MASSOUD·Filed 2006·Granted Jan 10, 2012·3 cites·18 claims
- 0565US7447101B2PG-gated data retention technique for reducing leakage in memory cellsFUJITSU LTD·Filed 2006·Granted Nov 4, 2008·6 cites·35 claims
- 0662US7613942B2Power mode transition in multi-threshold complementary metal oxide semiconductor (MTCMOS) circuitsFUJITSU LTD·Filed 2006·Granted Nov 3, 2009·4 cites·18 claims
- 0760US7834684B2Sizing and placement of charge recycling (CR) transistors in multithreshold complementary metal-oxide-semiconductor (MTCMOS) circuitsFUJITSU LTD·Filed 2008·Granted Nov 16, 2010·4 cites·24 claims
- 0855US6813700B2Reduction of bus switching activity using an encoder and decoderFUJITSU LTD·Filed 2002·Granted Nov 2, 2004·5 cites·30 claims
- 0954US6834335B2System and method for reducing transitions on address busesFUJITSU LTD·Filed 2002·Granted Dec 21, 2004·8 cites·24 claims
- 1051US11303281B2Efficient pipelined architecture for superconducting single flux quantum logic circuits utilizing dual clocksUNIV SOUTHERN CALIFORNIA·Filed 2021·Granted Apr 12, 2022·0 cites·31 claims
- 1151US2023281432A1System and method for hybrid arithmetic and logic processing of neural networksUNIV SOUTHERN CALIFORNIA·Filed 2022·Application pending·0 cites
- 1248US6907511B2Reducing transitions on address buses using instruction-set-aware system and methodUNIV SOUTHERN CALIFORNIA·Filed 2003·Granted Jun 14, 2005·1 cites·50 claims
- 1346US7236107B2System and method for identifying optimal encoding for a given traceFUJITSU LTD·Filed 2004·Granted Jun 26, 2007·2 cites·34 claims
- 1445US2023185537A1Design of high-performance and scalable montgomery modular multiplier circuitsUNIV SOUTHERN CALIFORNIA·Filed 2021·Application pending·0 cites
- 1536US2009146734A1Charge Recycling (CR) in Power Gated Complementary Metal-Oxide-Semiconductor (CMOS) Circuits and in Super Cutoff CMOS (SCCMOS) CircuitsFUJITSU LTD·Filed 2008·Application pending·0 cites
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