Inventor · disambiguated record
Matthew W. Baker
Also filed as: BAKER MATTHEW W · BAKER MATTHEW WAYNE
11 granted patents·1 pending application·59 citations·filing 2007–2014
89Inventor score
Top patents by PatentIndex Score
12 records- 0183US8122399B2Compiler for closed-loop 1×N VLSI designBOWERS BENJAMIN J·Filed 2008·Granted Feb 21, 2012·10 cites·11 claims
- 0282US8141016B2Integrated design for manufacturing for 1×N VLSI designCORREALE JR ANTHONY·Filed 2008·Granted Mar 20, 2012·13 cites·27 claims
- 0378US9558308B2Compiler for closed-loop 1×N VLSI designMENTOR GRAPHICS CORP·Filed 2014·Granted Jan 31, 2017·3 cites·16 claims
- 0476US7966598B2Top level hierarchy wiring via 1×N compilerIBM·Filed 2008·Granted Jun 21, 2011·9 cites·20 claims
- 0575US8887113B2Compiler for closed-loop 1xN VLSI designBOWERS BENJAMIN J·Filed 2012·Granted Nov 11, 2014·3 cites·14 claims
- 0673US8156458B2Uniquification and parent-child constructs for 1xN VLSI designBAKER MATTHEW W·Filed 2008·Granted Apr 10, 2012·9 cites·23 claims
- 0770US8136062B2Hierarchy reassembler for 1×N VLSI designSTEINMETZ PAUL M·Filed 2008·Granted Mar 13, 2012·7 cites·22 claims
- 0858US7882385B2Reducing inefficiencies of multi-clock-domain interfaces using a modified latch bankIBM·Filed 2007·Granted Feb 1, 2011·1 cites·20 claims
- 0956US8132134B2Closed-loop 1×N VLSI design systemCORREALE JR ANTHONY·Filed 2008·Granted Mar 6, 2012·1 cites·21 claims
- 1054US7672188B2System for blocking multiple memory read port activationIBM·Filed 2007·Granted Mar 2, 2010·3 cites·5 claims
- 1151US8739086B2Compiler for closed-loop 1×N VLSI designBOWERS BENJAMIN J·Filed 2012·Granted May 27, 2014·0 cites·5 claims
- 1247US2010107130A11xn block builder for 1xn vlsi designIBM·Filed 2008·Application pending·0 cites
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