Inventor · disambiguated record
Chin-Cheng Kau
Also filed as: KAU CHIN-CHENG
11 granted patents·394 citations·filing 1992–2001
92Inventor score
Top patents by PatentIndex Score
11 records- 0192US5467473AOut of order instruction load and store comparisonIBM·Filed 1993·Granted Nov 14, 1995·195 cites·19 claims
- 0286US6452592B2Clock generation for sampling analog videoSMARTASIC INC·Filed 2001·Granted Sep 17, 2002·28 cites·21 claims
- 0373US6310618B1Clock generation for sampling analong videoSMARTASIC INC·Filed 1998·Granted Oct 30, 2001·35 cites·16 claims
- 0464US5465373AMethod and system for single cycle dispatch of multiple instructions in a superscalar processor systemIBM·Filed 1993·Granted Nov 7, 1995·46 cites·7 claims
- 0553US5978896AMethod and system for increased instruction dispatch efficiency in a superscalar processor systemIBM·Filed 1994·Granted Nov 2, 1999·26 cites·8 claims
- 0646US5491829AMethod and system for indexing the assignment of intermediate storage buffers in a superscalar processor systemIBM·Filed 1995·Granted Feb 13, 1996·20 cites·6 claims
- 0742US5898882AMethod and system for enhanced instruction dispatch in a superscalar processor system utilizing independently accessed intermediate storageIBM·Filed 1993·Granted Apr 27, 1999·13 cites·10 claims
- 0842US5764942AMethod and system for selective serialization of instruction processing in a superscalar processor systemIBM·Filed 1996·Granted Jun 9, 1998·14 cites·8 claims
- 0940US5761473AMethod and system for increased instruction synchronization efficiency in a superscalar processsor system utilizing partial data dependency interlockingIBM·Filed 1993·Granted Jun 2, 1998·12 cites·4 claims
- 1031US5765221AMethod and system of addressing which minimize memory utilized to store logical addresses by storing high order bits within a registerIBM·Filed 1996·Granted Jun 9, 1998·3 cites·20 claims
- 1124US5341502ADevice for assigning a shared resource in a data processing systemMOTOROLA INC·Filed 1992·Granted Aug 23, 1994·2 cites·6 claims
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