Inventor

LIE FEE LI

US177 patents

⚠️ This page may combine multiple inventors who share the name “LIE FEE LI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIE FEE LI

IBM

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

Semiconductor microcooler

Inverse tone direct print EUV lithography enabled by selective material deposition

Self-aligned shallow trench isolation and doping for vertical fin transistors

Bottom source/drain silicidation for vertical field-effect transistor (FET)

Formation of a bottom source-drain for vertical field-effect transistors

Vertical transistor including a bottom source/drain region, a gate structure, and an air gap formed between the bottom source/drain region and the gate structure

Single spacer for complementary metal oxide semiconductor process flow

Method to form dual channel semiconductor material fins

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

Registration mark formation during sidewall image transfer process

Self-aligned quadruple patterning process

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

Method and structure for enabling high aspect ratio sacrificial gates

Nanosheet channel-to-source and drain isolation

Semiconductor microcooler

Controlling gate profile by inter-layer dielectric (ILD) nanolaminates

Nanosheet channel-to-source and drain isolation

Silicidation of bottom source/drain sheet using pinch-off sacrificial spacer process

Forming stacked nanowire semiconductor device

Air gap spacer for metal gates

Vertical transport field effect transistor with precise gate length definition

Vertical FET structure

Preventing strained fin relaxation

Method and structure for enabling high aspect ratio sacrificial gates

Method to form dual channel semiconductor material fins

Merged gate for vertical transistors

Dummy gate formation using spacer pull down hardmask

Method and structure for enabling high aspect ratio sacrificial gates

FinFET device with channel strain

Forming semiconductor fins with self-aligned patterning

Pitch scalable active area patterning structure and process for multi-channel finFET technologies

Preventing strained fin relaxation by sealing fin ends

Channel protection during fin fabrication

Multiple threshold voltage FinFETs

FinFET device with channel strain

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Semiconductor device and method of forming the semiconductor device

Non volatile resistive memory logic device

Vertical transistor and method of forming the vertical transistor

Patterning magnetic tunnel junctions and the like while reducing detrimental resputtering of underlying features

Sublithography gate cut physical unclonable function

TESSERA LLC

Two-color self-aligned double patterning (SADP) to yield static random access memory (SRAM) and dense logic

Nanosheet channel-to-source and drain isolation

Air gap spacer for metal gates

TESSERA INC

Nanosheet channel-to-source and drain isolation