Inventor · disambiguated record
Zachary Geiger
Also filed as: GEIGER ZACHARY
7 granted patents·2 pending applications·6 citations·filing 2019–2025
76Inventor score
Files withINTEL CORP9
Top patents by PatentIndex Score
9 records- 0184US11532734B2Gate-all-around integrated circuit structures having germanium nanowire channel structuresINTEL CORP·Filed 2019·Granted Dec 20, 2022·3 cites·26 claims
- 0281US11244943B2Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel materialINTEL CORP·Filed 2019·Granted Feb 8, 2022·2 cites·21 claims
- 0379US2025113550A1Gate-all-around integrated circuit structures having nanowires with tight vertical spacingINTEL CORP·Filed 2024·Application pending·0 cites
- 0478US12206027B2Gate-all-around integrated circuit structures having nanowires with tight vertical spacingINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 0574US11769836B2Gate-all-around integrated circuit structures having nanowires with tight vertical spacingINTEL CORP·Filed 2019·Granted Sep 26, 2023·1 cites·23 claims
- 0672US11978784B2Gate-all-around integrated circuit structures having germanium nanowire channel structuresINTEL CORP·Filed 2022·Granted May 7, 2024·0 cites·25 claims
- 0770US2025204032A1Selective growth self-aligned gate endcap (sage) architectures without fin end gapINTEL CORP·Filed 2025·Application pending·0 cites
- 0869US11996404B2Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel materialINTEL CORP·Filed 2021·Granted May 28, 2024·0 cites·18 claims
- 0961US12272688B2Selective growth self-aligned gate endcap (SAGE) architectures without fin end gapINTEL CORP·Filed 2020·Granted Apr 8, 2025·0 cites·14 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →