Inventor · disambiguated record
Wai-Kei Mak
Also filed as: MAK WAI KWAN · MAK WAI-KEI
12 granted patents·3 pending applications·18 citations·filing 2002–2025
86Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD8CHANG FONG-YUAN2SYNOPSYS INC2NAT UNIV TSING HUA1SYNOPSYS TAIWAN CO LTD1
Top patents by PatentIndex Score
15 records- 0187US11062076B2Method and system of generating a layout diagramTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 13, 2021·2 cites·20 claims
- 0284US10776551B2Method and system of revising a layout diagramTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 15, 2020·3 cites·20 claims
- 0374US8407647B2Systems and methods for designing and making integrated circuits with consideration of wiring demand ratioCHANG FONG-YUAN·Filed 2010·Granted Mar 26, 2013·3 cites·12 claims
- 0473US2025307517A1Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0572US8875081B2Systems and methods for designing and making integrated circuits with consideration of wiring demand ratioSYNOPSYS TAIWAN CO LTD·Filed 2013·Granted Oct 28, 2014·2 cites·10 claims
- 0672US2025061261A1Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 0770US7917880B2Method for reducing power consumption of integrated circuitNAT UNIV TSING HUA·Filed 2008·Granted Mar 29, 2011·5 cites·12 claims
- 0869US11741286B2Method and system of generating a layout diagramTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 0965US12164854B2Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Dec 10, 2024·0 cites·20 claims
- 1065US8336001B2Method for improving yield rate using redundant wire insertionCHANG FONG-YUAN·Filed 2010·Granted Dec 18, 2012·2 cites·12 claims
- 1164US10192019B2Separation and minimum wire length constrained maze routing method and systemSYNOPSYS INC·Filed 2014·Granted Jan 29, 2019·1 cites·17 claims
- 1263US12387027B2Method, non-transitory computer-readable medium, and apparatus for arranging electrical components within a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 12, 2025·0 cites·20 claims
- 1358US9665679B2Systems and methods for designing integrated circuits with consideration of horizontal and vertical wiring demand ratiosSYNOPSYS INC·Filed 2014·Granted May 30, 2017·0 cites·14 claims
- 1443US10474038B2Method, system, and storage medium for resolving coloring conflict in multi-patterning lithographyTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Nov 12, 2019·0 cites·20 claims
- 1533US2003226037A1Authorization negotiation in multi-domain environmentFiled 2002·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →