Inventor · disambiguated record
Edward T. Grochowski
Also filed as: GROCHOWSKI EDWARD · GROCHOWSKI EDWARD T · GROCHOWSKI EDWARD THOMAS
115 granted patents·21 pending applications·3,058 citations·filing 1989–2024
99Inventor score
Top patents by PatentIndex Score
136 records- 0198US10275243B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2016·Granted Apr 30, 2019·23 cites·20 claims
- 0297US11093277B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·25 claims
- 0397US10146535B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2016·Granted Dec 4, 2018·23 cites·22 claims
- 0497US6564328B1Microprocessor with digital power throttleINTEL CORP·Filed 1999·Granted May 13, 2003·352 cites·25 claims
- 0596US11698787B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2021·Granted Jul 11, 2023·3 cites·17 claims
- 0696US11693691B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2021·Granted Jul 4, 2023·4 cites·11 claims
- 0796US11487541B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2020·Granted Nov 1, 2022·4 cites·34 claims
- 0896US9170955B2Providing extended cache replacement state informationINTEL CORP·Filed 2012·Granted Oct 27, 2015·59 cites·23 claims
- 0996US7437581B2Method and apparatus for varying energy per instruction according to the amount of available parallelismINTEL CORP·Filed 2004·Granted Oct 14, 2008·138 cites·50 claims
- 1095US10234930B2Performing power management in a multicore processorINTEL CORP·Filed 2015·Granted Mar 19, 2019·20 cites·24 claims
- 1195US6615366B1Microprocessor with dual execution core operable in high reliability modeINTEL CORP·Filed 1999·Granted Sep 2, 2003·292 cites·24 claims
- 1294US6636976B1Mechanism to control di/dt for a microprocessorINTEL CORP·Filed 2000·Granted Oct 21, 2003·127 cites·19 claims
- 1393US11113053B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2019·Granted Sep 7, 2021·8 cites·20 claims
- 1493US10585667B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2018·Granted Mar 10, 2020·7 cites·18 claims
- 1593US10489063B2Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplicationINTEL CORP·Filed 2016·Granted Nov 26, 2019·10 cites·20 claims
- 1692US10282296B2Zeroing a cache lineINTEL CORP·Filed 2016·Granted May 7, 2019·7 cites·22 claims
- 1792US9513917B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2014·Granted Dec 6, 2016·10 cites·14 claims
- 1892US7236920B2Mechanism for estimating and controlling di/dt-induced power supply voltage variationsINTEL CORP·Filed 2005·Granted Jun 26, 2007·25 cites·17 claims
- 1991US11416281B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2016·Granted Aug 16, 2022·4 cites·28 claims
- 2091US7480838B1Method, system and apparatus for detecting and recovering from timing errorsINTEL CORP·Filed 2006·Granted Jan 20, 2009·29 cites·10 claims
- 2190US12135981B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2023·Granted Nov 5, 2024·1 cites·20 claims
- 2290US6678815B1Apparatus and method for reducing power consumption due to cache and TLB accesses in a processor front-endINTEL CORP·Filed 2000·Granted Jan 13, 2004·67 cites·16 claims
- 2389US6931559B2Multiple mode power throttle mechanismINTEL CORP·Filed 2001·Granted Aug 16, 2005·67 cites·19 claims
- 2488US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 2588US7622961B2Method and apparatus for late timing transition detectionINTEL CORP·Filed 2005·Granted Nov 24, 2009·15 cites·7 claims
- 2688US6367023B2Method and apparatus of measuring current, voltage, or duty cycle of a power supply to manage power consumption in a computer systemINTEL CORP·Filed 1998·Granted Apr 2, 2002·132 cites·23 claims
- 2788US2024427600A1Vector friendly instruction format and execution thereofINTEL CORP·Filed 2024·Application pending·0 cites
- 2887US10853065B2Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2018·Granted Dec 1, 2020·3 cites·22 claims
- 2987US2025138823A1Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2024·Application pending·0 cites
- 3086US5442756ABranch prediction and resolution apparatus for a superscalar computer processorINTEL CORP·Filed 1992·Granted Aug 15, 1995·101 cites·15 claims
- 3185US6928645B2Software-based speculative pre-computation and multithreadingINTEL CORP·Filed 2001·Granted Aug 9, 2005·48 cites·16 claims
- 3284US12086594B2Vector friendly instruction format and execution thereofINTEL CORP·Filed 2023·Granted Sep 10, 2024·0 cites·23 claims
- 3384US8533436B2Adaptively handling remote atomic execution based upon contention predictionFRYMAN JOSHUA B·Filed 2009·Granted Sep 10, 2013·17 cites·20 claims
- 3484US5606676ABranch prediction and resolution apparatus for a superscalar computer processorINTEL CORP·Filed 1995·Granted Feb 25, 1997·103 cites·13 claims
- 3583US2025060963A1Systems, apparatuses, and methods for chained fused multiply addINTEL CORP·Filed 2024·Application pending·0 cites
- 3682US12204898B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·24 claims
- 3782US11294809B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2018·Granted Apr 5, 2022·2 cites·7 claims
- 3882US9898286B2Packed finite impulse response (FIR) filter processors, methods, systems, and instructionsINTEL CORP·Filed 2015·Granted Feb 20, 2018·4 cites·25 claims
- 3982US7035785B2Mechanism for estimating and controlling di/dt-induced power supply voltage variationsINTEL CORP·Filed 2001·Granted Apr 25, 2006·27 cites·22 claims
- 4082US6732260B1Presbyopic branch target prefetch method and apparatusINTEL CORP·Filed 2000·Granted May 4, 2004·31 cites·30 claims
- 4182US6035389AScheduling instructions with different latenciesINTEL CORP·Filed 1998·Granted Mar 7, 2000·98 cites·47 claims
- 4282US2025123881A1Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2024·Application pending·0 cites
- 4381US12050912B2Interruptible and restartable matrix multiplication instructions, processors, methods, and systemsINTEL CORP·Filed 2023·Granted Jul 30, 2024·0 cites·20 claims
- 4481US9465670B2Generational thread scheduler using reservations for fair schedulingGROCHOWSKI EDWARD T·Filed 2011·Granted Oct 11, 2016·7 cites·20 claims
- 4581US6564332B1Method and apparatus for managing power consumption in a computer system responsive to the power delivery specifications of a power outletINTEL CORP·Filed 1998·Granted May 13, 2003·92 cites·17 claims
- 4680US7340643B2Replay mechanism for correcting soft errorsINTEL CORP·Filed 2003·Granted Mar 4, 2008·26 cites·5 claims
- 4780US7281140B2Digital throttle for multiple operating pointsINTEL CORP·Filed 2001·Granted Oct 9, 2007·31 cites·26 claims
- 4880US6754689B2Method and apparatus for performing subtraction in redundant form arithmeticINTEL CORP·Filed 2000·Granted Jun 22, 2004·29 cites·30 claims
- 4980US6021500AProcessor with sleep and deep sleep modesINTEL CORP·Filed 1997·Granted Feb 1, 2000·97 cites·20 claims
- 5079US8125246B2Method and apparatus for late timing transition detectionGROCHOWSKI EDWARD·Filed 2009·Granted Feb 28, 2012·9 cites·18 claims
Showing the top 50 of 136 patent records by PatentIndex Score.
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