Inventor · disambiguated record
Mark D. Crook
Also filed as: CROOK MARK D · CROOK MARK J
8 granted patents·3 pending applications·198 citations·filing 1990–2008
86Inventor score
Files withAGILENT TECHNOLOGIES INC2APTINA IMAGING CORP2HEWLETT PACKARD CO2PALSULE CHINTAMANI2APTINA IMAGING CORP INC1
Top patents by PatentIndex Score
11 records- 0191US7208783B2Optical enhancement of integrated circuit photodetectorsMICRON TECHNOLOGY INC·Filed 2004·Granted Apr 24, 2007·50 cites·28 claims
- 0284US5110712AIncorporation of dielectric layers in a semiconductorHEWLETT PACKARD CO·Filed 1990·Granted May 5, 1992·114 cites·9 claims
- 0359US7459733B2Optical enhancement of integrated circuit photodetectorsAPTINA IMAGING CORP·Filed 2007·Granted Dec 2, 2008·1 cites·14 claims
- 0459US6646346B1Integrated circuit metallization using a titanium/aluminum alloyAGILENT TECHNOLOGIES INC·Filed 2000·Granted Nov 11, 2003·7 cites·5 claims
- 0553US5084414AMetal interconnection system with a planar surfaceHEWLETT PACKARD CO·Filed 1990·Granted Jan 28, 1992·25 cites·3 claims
- 0652US7704780B2Optical enhancement of integrated circuit photodetectorsAPTINA IMAGING CORP·Filed 2008·Granted Apr 27, 2010·0 cites·11 claims
- 0749US7768084B2Shallow semiconductor sensor with fluorescent molecule layer that eliminates optical and electronic crosstalkAPTINA IMAGING CORP INC·Filed 2006·Granted Aug 3, 2010·0 cites·10 claims
- 0844US6903017B2Integrated circuit metallization using a titanium/aluminum alloyAGILENT TECHNOLOGIES INC·Filed 2003·Granted Jun 7, 2005·1 cites·4 claims
- 0944US2007020920A1Method for fabricating low leakage interconnect layers in integrated circuitsPALSULE CHINTAMANI·Filed 2006·Application pending·0 cites
- 1038US2006099800A1Method for fabricating low leakage interconnect layers in integrated circuitsPALSULE CHINTAMANI·Filed 2004·Application pending·0 cites
- 1135US2007256750A1CentraliserU W G LTD·Filed 2007·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →