Inventor · disambiguated record
Konrad K. Lai
Also filed as: LAI KONRAD · LAI KONRAD K
60 granted patents·11 pending applications·2,683 citations·filing 1986–2022
99Inventor score
Top patents by PatentIndex Score
71 records- 0197US8479053B2Processor with last branch record register storing transaction indicatorRAJWAR RAVI·Filed 2010·Granted Jul 2, 2013·55 cites·22 claims
- 0295US8301849B2Transactional memory in out-of-order processors with XABORT having immediate argumentRAJWAR RAVI·Filed 2009·Granted Oct 30, 2012·40 cites·20 claims
- 0395US8180977B2Transactional memory in out-of-order processorsRAJWAR RAVI·Filed 2006·Granted May 15, 2012·48 cites·31 claims
- 0495US5617554APhysical address size selection and page size selection in an address translatorINTEL CORP·Filed 1994·Granted Apr 1, 1997·198 cites·28 claims
- 0595US5075848AObject lifetime control in an object-oriented memory protection mechanismINTEL CORP·Filed 1989·Granted Dec 24, 1991·199 cites·3 claims
- 0695US5075842ADisabling tag bit recognition and allowing privileged operations to occur in an object-oriented memory protection mechanismINTEL CORP·Filed 1989·Granted Dec 24, 1991·196 cites·4 claims
- 0791USRE38388EMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 2001·Granted Jan 13, 2004·50 cites·73 claims
- 0890US10409612B2Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·7 cites·20 claims
- 0990US5493667AApparatus and method for an instruction cache locking schemeINTEL CORP·Filed 1993·Granted Feb 20, 1996·162 cites·67 claims
- 1087US6757784B2Hiding refresh of memory and refresh-hidden memoryINTEL CORP·Filed 2001·Granted Jun 29, 2004·44 cites·15 claims
- 1186US5548742AMethod and apparatus for combining a direct-mapped cache and a multiple-way cache in a cache memoryINTEL CORP·Filed 1994·Granted Aug 20, 1996·110 cites·32 claims
- 1285US5564035AExclusive and/or partially inclusive extension cache system and method to minimize swapping thereinINTEL CORP·Filed 1994·Granted Oct 8, 1996·111 cites·24 claims
- 1385US5550988AApparatus and method for performing error correction in a multi-processor systemINTEL CORP·Filed 1994·Granted Aug 27, 1996·105 cites·34 claims
- 1485US4811208AStack frame cache on a microprocessor chipINTEL CORP·Filed 1986·Granted Mar 7, 1989·101 cites·3 claims
- 1584US5581782AComputer system with distributed bus arbitration scheme for symmetric and priority agentsINTEL CORP·Filed 1995·Granted Dec 3, 1996·117 cites·48 claims
- 1683US8972994B2Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environmentSRINIVAS SURESH·Filed 2009·Granted Mar 3, 2015·15 cites·17 claims
- 1783US8180967B2Transactional memory virtualizationRAJWAR RAVI·Filed 2006·Granted May 15, 2012·12 cites·33 claims
- 1883US7020766B1Processing essential and non-essential code separatelyINTEL CORP·Filed 2000·Granted Mar 28, 2006·34 cites·37 claims
- 1983US6725341B1Cache line pre-load and pre-own based on cache coherence speculationINTEL CORP·Filed 2000·Granted Apr 20, 2004·32 cites·23 claims
- 2083US5615343AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1994·Granted Mar 25, 1997·69 cites·31 claims
- 2182US6006299AApparatus and method for caching lock conditions in a multi-processor systemINTEL CORP·Filed 1994·Granted Dec 21, 1999·94 cites·15 claims
- 2281US7076613B2Cache line pre-load and pre-own based on cache coherence speculationINTEL CORP·Filed 2004·Granted Jul 11, 2006·28 cites·17 claims
- 2380US10073719B2Last branch record indicators for transactional memoryINTEL CORP·Filed 2016·Granted Sep 11, 2018·2 cites·19 claims
- 2480US5796977AHighly pipelined bus architectureINTEL CORP·Filed 1996·Granted Aug 18, 1998·89 cites·16 claims
- 2579US4891753ARegister scorboarding on a microprocessor chipINTEL CORP·Filed 1986·Granted Jan 2, 1990·69 cites·3 claims
- 2678US4823260AMixed-precision floating point operations from a single instruction opcodeINTEL CORP·Filed 1987·Granted Apr 18, 1989·66 cites·4 claims
- 2777US6507895B1Method and apparatus for access demarcationINTEL CORP·Filed 2000·Granted Jan 14, 2003·25 cites·25 claims
- 2877US5715428AApparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer systemINTEL CORP·Filed 1996·Granted Feb 3, 1998·82 cites·35 claims
- 2977US5075845AType management and control in an object oriented memory protection mechanismINTEL CORP·Filed 1989·Granted Dec 24, 1991·58 cites·3 claims
- 3076US5157777ASynchronous communication between execution environments in a data processing system employing an object-oriented memory protection mechanismINTEL CORP·Filed 1991·Granted Oct 20, 1992·73 cites·5 claims
- 3175US6608775B2Register file schemeINTEL CORP·Filed 2002·Granted Aug 19, 2003·18 cites·12 claims
- 3275US6430083B1Register file schemeINTEL CORP·Filed 2000·Granted Aug 6, 2002·18 cites·13 claims
- 3372US6671780B1Modified least recently allocated cache replacement method and apparatus that allows skipping a least recently allocated cache blockINTEL CORP·Filed 2000·Granted Dec 30, 2003·16 cites·18 claims
- 3472US5568620AMethod and apparatus for performing bus transactions in a computer systemINTEL CORP·Filed 1993·Granted Oct 22, 1996·58 cites·33 claims
- 3571US5903908AMethod and apparatus for maintaining cache coherency using a single controller for multiple cache memoriesINTEL CORP·Filed 1996·Granted May 11, 1999·60 cites·13 claims
- 3671US5832534AMethod and apparatus for maintaining cache coherency using a single controller for multiple cache memoriesINTEL CORP·Filed 1995·Granted Nov 3, 1998·43 cites·6 claims
- 3771US5802605APhysical address size selection and page size selection in an address translatorINTEL CORP·Filed 1996·Granted Sep 1, 1998·52 cites·18 claims
- 3870US8881106B2Debugging parallel software using speculatively executed code sequences in a multiple core environmentLACHNER PETER·Filed 2010·Granted Nov 4, 2014·3 cites·21 claims
- 3970US7437542B2Identifying and processing essential and non-essential code separatelyINTEL CORP·Filed 2006·Granted Oct 14, 2008·4 cites·32 claims
- 4067US8782382B2Last branch record indicators for transactional memoryINTEL CORP·Filed 2013·Granted Jul 15, 2014·1 cites·20 claims
- 4166US9529645B2Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target codeINTEL CORP·Filed 2015·Granted Dec 27, 2016·1 cites·17 claims
- 4266US8924692B2Event counter checkpointing and restoringKNAUTH LAURA A·Filed 2009·Granted Dec 30, 2014·3 cites·23 claims
- 4363US5678020AMemory subsystem wherein a single processor chip controls multiple cache memory chipsINTEL CORP·Filed 1996·Granted Oct 14, 1997·36 cites·24 claims
- 4462US6711662B2Multiprocessor cache coherence managementINTEL CORP·Filed 2001·Granted Mar 23, 2004·9 cites·25 claims
- 4560US10331452B2Tracking mode of a processing device in instruction tracing systemsINTEL CORP·Filed 2013·Granted Jun 25, 2019·1 cites·16 claims
- 4660US10261879B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Apr 16, 2019·0 cites·13 claims
- 4760US10210066B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Feb 19, 2019·0 cites·9 claims
- 4860US10152401B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Dec 11, 2018·0 cites·8 claims
- 4960US5937171AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1996·Granted Aug 10, 1999·26 cites·43 claims
- 5059US10248524B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Apr 2, 2019·0 cites·12 claims
Showing the top 50 of 71 patent records by PatentIndex Score.
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