Inventor
RAJWAR RAVI
US49 patents
⚠️ This page may combine multiple inventors who share the name “RAJWAR RAVI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
25 patentsUS7685365B2Mar 23, 2010
Transactional memory execution utilizing virtual memory
INTEL CORP430 citations99
US7809903B2Oct 5, 2010
Coordinating access to memory locations for hardware transactional memory transactions and software transactional memory transactions
INTEL CORP17 citations84
US10409612B2Sep 10, 2019
Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative execution
INTEL CORP7 citations82
US9665373B2May 30, 2017
Protecting confidential data with transactional processing in execute-only memory
INTEL CORP2 citations73
US7711932B2May 4, 2010
Scalable rename map table recovery
INTEL CORP6 citations73
US10073719B2Sep 11, 2018
Last branch record indicators for transactional memory
INTEL CORP2 citations72
US10146538B2Dec 4, 2018
Suspendable load address tracking inside transactions
INTEL CORP2 citations71
US8782382B2Jul 15, 2014
Last branch record indicators for transactional memory
INTEL CORP1 citations62
US10331452B2Jun 25, 2019
Tracking mode of a processing device in instruction tracing systems
INTEL CORP1 citations60
US10261879B2Apr 16, 2019
Instruction and logic to test transactional execution status
INTEL CORP0 citations52
US10248524B2Apr 2, 2019
Instruction and logic to test transactional execution status
INTEL CORP0 citations52
US10223227B2Mar 5, 2019
Instruction and logic to test transactional execution status
INTEL CORP0 citations52
US10210065B2Feb 19, 2019
Instruction and logic to test transactional execution status
INTEL CORP0 citations52
US10210066B2Feb 19, 2019
Instruction and logic to test transactional execution status
INTEL CORP0 citations52
US10152401B2Dec 11, 2018
Instruction and logic to test transactional execution status
INTEL CORP0 citations52
US7487337B2Feb 3, 2009
Back-end renaming in a continual flow processor pipeline
INTEL CORP1 citations52
US9529645B2Dec 27, 2016
Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code
INTEL CORP1 citations51
US9411739B2Aug 9, 2016
System, method and apparatus for improving transactional memory (TM) throughput using TM region indicators
INTEL CORP1 citations51
US9354878B2May 31, 2016
Last branch record register for storing taken branch information and transactional memory transaction indicator to be used in transaction execution analysis
INTEL CORP0 citations51
US7900023B2Mar 1, 2011
Technique to enable store forwarding during long latency instruction execution
INTEL CORP0 citations51
US10409611B2Sep 10, 2019
Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative execution
INTEL CORP0 citations50
US10241952B2Mar 26, 2019
Throttling integrated link
INTEL CORP0 citations50
US9535744B2Jan 3, 2017
Method and apparatus for continued retirement during commit of a speculative region of code
INTEL CORP1 citations50
US9372764B2Jun 21, 2016
Event counter checkpointing and restoring
INTEL CORP0 citations49
US9311241B2Apr 12, 2016
Method and apparatus to write modified cache data to a backing store while retaining write permissions
INTEL CORP0 citations48
RAJWAR RAVI
8 patentsUS8479053B2Jul 2, 2013
Processor with last branch record register storing transaction indicator
RAJWAR RAVI55 citations96
US8301849B2Oct 30, 2012
Transactional memory in out-of-order processors with XABORT having immediate argument
RAJWAR RAVI40 citations94
US8180977B2May 15, 2012
Transactional memory in out-of-order processors
RAJWAR RAVI48 citations93
US8180967B2May 15, 2012
Transactional memory virtualization
RAJWAR RAVI12 citations82
US9182986B2Nov 10, 2015
Copy-on-write buffer for restoring program code from a speculative region to a non-speculative region
RAJWAR RAVI7 citations77
US9268596B2Feb 23, 2016
Instruction and logic to test transactional execution status
RAJWAR RAVI0 citations52
US8996845B2Mar 31, 2015
Vector compare-and-exchange operation
RAJWAR RAVI1 citations52
US9146610B2Sep 29, 2015
Throttling integrated link
RAJWAR RAVI1 citations50
WISCONSIN ALUMNI RES FOUND
5 patentsUS7120762B2Oct 10, 2006
Concurrent execution of critical sections by eliding ownership of locks
WISCONSIN ALUMNI RES FOUND100 citations98
US6460124B1Oct 1, 2002
Method of using delays to speed processing of inferred critical program portions
WISCONSIN ALUMNI RES FOUND75 citations96
US7765364B2Jul 27, 2010
Concurrent execution of critical sections by eliding ownership of locks
WISCONSIN ALUMNI RES FOUND17 citations92
US7340569B2Mar 4, 2008
Computer architecture providing transactional, lock-free execution of lock-based programs
WISCONSIN ALUMNI RES FOUND12 citations84
US7962699B2Jun 14, 2011
Concurrent execution of critical sections by eliding ownership of locks
WISCONSIN ALUMNI RES FOUND4 citations63
AKKARY HAITHAM
4 patentsUS8627030B2Jan 7, 2014
Late lock acquire mechanism for hardware lock elision (HLE)
AKKARY HAITHAM7 citations83
US8190859B2May 29, 2012
Critical section detection and prediction mechanism for hardware lock elision
AKKARY HAITHAM15 citations83
US9798590B2Oct 24, 2017
Post-retire scheme for tracking tentative accesses during transactional execution
AKKARY HAITHAM2 citations72
US9262173B2Feb 16, 2016
Critical section detection and prediction mechanism for hardware lock elision
AKKARY HAITHAM1 citations51