Inventor · disambiguated record
Bernard C. Drerup
Also filed as: DRERUP BERNARD · DRERUP BERNARD C · DRERUP BERNARD CHARLES
88 granted patents·3 pending applications·974 citations·filing 1991–2021
99Inventor score
Files withIBM81ARIMILLI LAKSHMINARAYANA B4BIRMIWAL PARAG2DRERUP BERNARD CHARLES2ARIMILLI LAKSHMINARAYANA1
Top patents by PatentIndex Score
91 records- 0195US9342387B1Hardware-assisted interthread push communicationIBM·Filed 2015·Granted May 17, 2016·13 cites·6 claims
- 0294US9753862B1Hybrid replacement policy in a multilevel cache memory hierarchyIBM·Filed 2016·Granted Sep 5, 2017·11 cites·13 claims
- 0393US7620749B2Descriptor prefetch mechanism for high latency and out of order DMA deviceIBM·Filed 2007·Granted Nov 17, 2009·49 cites·11 claims
- 0492US9727489B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Aug 8, 2017·8 cites·18 claims
- 0592US9286148B1Hardware-assisted interthread push communicationIBM·Filed 2014·Granted Mar 15, 2016·13 cites·13 claims
- 0692US7136954B2Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanismIBM·Filed 2005·Granted Nov 14, 2006·25 cites·16 claims
- 0791US7647435B2Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanismIBM·Filed 2007·Granted Jan 12, 2010·20 cites·14 claims
- 0890US9727488B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Aug 8, 2017·7 cites·18 claims
- 0990US8077602B2Performing dynamic request routing based on broadcast queue depthsARIMILLI LAKSHMINARAYANA B·Filed 2008·Granted Dec 13, 2011·23 cites·21 claims
- 1087US7779148B2Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chipsIBM·Filed 2008·Granted Aug 17, 2010·15 cites·18 claims
- 1184US10671539B2Cache line replacement using reference states based on data reference attributesIBM·Filed 2018·Granted Jun 2, 2020·3 cites·20 claims
- 1284US9575825B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Feb 21, 2017·6 cites·10 claims
- 1384US7523228B2Method for performing a direct memory access block move in a direct memory access deviceIBM·Filed 2006·Granted Apr 21, 2009·16 cites·16 claims
- 1484US7249207B2Internal data bus interconnection mechanism utilizing central interconnection module converting data in different alignment domainsIBM·Filed 2005·Granted Jul 24, 2007·14 cites·18 claims
- 1583US6826656B2Reducing power in a snooping cache based multiprocessor environmentIBM·Filed 2002·Granted Nov 30, 2004·35 cites·27 claims
- 1682US11561901B1Distribution of injected data among caches of a data processing systemIBM·Filed 2021·Granted Jan 24, 2023·1 cites·19 claims
- 1782US11556472B1Data processing system having masters that adapt to agents with differing retry behaviorsIBM·Filed 2021·Granted Jan 17, 2023·1 cites·19 claims
- 1882US9940239B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Apr 10, 2018·4 cites·12 claims
- 1982US7882278B2Utilizing programmable channels for allocation of buffer space and transaction control in data communicationsIBM·Filed 2009·Granted Feb 1, 2011·10 cites·20 claims
- 2082US7493426B2Data communication method and apparatus utilizing programmable channels for allocation of buffer space and transaction controlIBM·Filed 2005·Granted Feb 17, 2009·10 cites·12 claims
- 2181US8281075B2Processor system and methods of triggering a block move using a system bus write command initiated by user codeARIMILLI LAKSHMINARAYANA BABA·Filed 2009·Granted Oct 2, 2012·10 cites·20 claims
- 2279US10191847B2Prefetch performanceIBM·Filed 2017·Granted Jan 29, 2019·2 cites·20 claims
- 2379US7996614B2Cache intervention on a separate data bus when on-chip bus has separate read and write data bussesIBM·Filed 2008·Granted Aug 9, 2011·9 cites·18 claims
- 2479US7669013B2Directory for multi-node coherent busIBM·Filed 2007·Granted Feb 23, 2010·9 cites·20 claims
- 2579US7603490B2Barrier and interrupt mechanism for high latency and out of order DMA deviceIBM·Filed 2007·Granted Oct 13, 2009·10 cites·20 claims
- 2678US5898885AMethod and system for executing a non-native stack-based instruction within a computer systemIBM·Filed 1997·Granted Apr 27, 1999·93 cites·13 claims
- 2778US5875336AMethod and system for translating a non-native bytecode to a set of codes native to a processor within a computer systemIBM·Filed 1997·Granted Feb 23, 1999·89 cites·16 claims
- 2875US7065595B2Method and apparatus for bus access allocationIBM·Filed 2003·Granted Jun 20, 2006·21 cites·40 claims
- 2974US7277974B2Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanismIBM·Filed 2006·Granted Oct 2, 2007·5 cites·12 claims
- 3073US7093058B2Single request data transfer regardless of size and alignmentIBM·Filed 2005·Granted Aug 15, 2006·6 cites·4 claims
- 3173US6834378B2System on a chip bus with automatic pipeline stage insertion for timing closureIBM·Filed 2002·Granted Dec 21, 2004·15 cites·11 claims
- 3273US5740364ASystem and method for controlling data transfer between multiple interconnected computer systems with a portable input deviceIBM·Filed 1996·Granted Apr 14, 1998·69 cites·12 claims
- 3372US9766890B2Non-serialized push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Sep 19, 2017·2 cites·14 claims
- 3472US8417778B2Collective acceleration unit tree flow control and retransmitARIMILLI LAKSHMINARAYANA B·Filed 2009·Granted Apr 9, 2013·5 cites·19 claims
- 3570US7035958B2Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the targetIBM·Filed 2002·Granted Apr 25, 2006·15 cites·21 claims
- 3669US7827428B2System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architectureIBM·Filed 2007·Granted Nov 2, 2010·4 cites·25 claims
- 3769US5579481ASystem and method for controlling data transfer between multiple interconnected computer systems with an untethered stylusIBM·Filed 1995·Granted Nov 26, 1996·55 cites·12 claims
- 3868US9665297B1Injection of at least a partial cache line in a private multilevel cache hierarchyIBM·Filed 2016·Granted May 30, 2017·1 cites·20 claims
- 3968US8751655B2Collective acceleration unit tree structureARIMILLI LAKSHMINARAYANA B·Filed 2010·Granted Jun 10, 2014·2 cites·22 claims
- 4068US6970962B2Transfer request pipeline throttlingIBM·Filed 2003·Granted Nov 29, 2005·13 cites·19 claims
- 4167US7127562B2Ensuring orderly forward progress in granting snoop castout requestsIBM·Filed 2003·Granted Oct 24, 2006·12 cites·12 claims
- 4266US9940246B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Apr 10, 2018·1 cites·15 claims
- 4366US7865644B2Method and apparatus for attaching multiple slave devices to a single bus controller interface while supporting command pipeliningIBM·Filed 2007·Granted Jan 4, 2011·3 cites·17 claims
- 4465US8302109B2Synchronization optimized queuing systemARIMILLI LAKSHMINARAYANA·Filed 2009·Granted Oct 30, 2012·5 cites·15 claims
- 4565US8266386B2Structure for maintaining memory data integrity in a processor integrated circuit using cache coherency protocolsDRERUP BERNARD CHARLES·Filed 2008·Granted Sep 11, 2012·4 cites·30 claims
- 4665US6907502B2Method for moving snoop pushes to the front of a request queueIBM·Filed 2002·Granted Jun 14, 2005·10 cites·27 claims
- 4765US5333285ASystem crash detect and automatic reset mechanism for processor cardsIBM·Filed 1991·Granted Jul 26, 1994·41 cites·14 claims
- 4863US7328312B2Method and bus prefetching mechanism for implementing enhanced buffer controlIBM·Filed 2005·Granted Feb 5, 2008·2 cites·3 claims
- 4962US6976132B2Reducing latency of a snoop tenureIBM·Filed 2003·Granted Dec 13, 2005·8 cites·20 claims
- 5062US6973520B2System and method for providing improved bus utilization via target directed completionIBM·Filed 2002·Granted Dec 6, 2005·8 cites·23 claims
Showing the top 50 of 91 patent records by PatentIndex Score.
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