Inventor · disambiguated record
David Karchmer
Also filed as: KARCHMER DAVID
27 granted patents·454 citations·filing 1995–2013
97Inventor score
Top patents by PatentIndex Score
27 records- 0195US7669157B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesALTERA CORP·Filed 2006·Granted Feb 23, 2010·28 cites·21 claims
- 0294US6026226ALocal compilation in context within a design hierarchyALTERA CORP·Filed 1997·Granted Feb 15, 2000·157 cites·38 claims
- 0391US7275232B2Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuitsALTERA CORP·Filed 2005·Granted Sep 25, 2007·24 cites·12 claims
- 0487US7853911B1Method and apparatus for performing path-level skew optimization and analysis for a logic designALTERA CORP·Filed 2005·Granted Dec 14, 2010·15 cites·36 claims
- 0586US7784008B1Performance visualization systemALTERA CORP·Filed 2006·Granted Aug 24, 2010·20 cites·25 claims
- 0686US7584443B1Clock domain conflict analysis for timing graphsALTERA CORP·Filed 2007·Granted Sep 1, 2009·19 cites·27 claims
- 0782US7464362B1Method and apparatus for performing incremental compilationALTERA CORP·Filed 2006·Granted Dec 9, 2008·12 cites·17 claims
- 0881US8572530B1Method and apparatus for performing path-level skew optimization and analysis for a logic designFUNG RYAN·Filed 2010·Granted Oct 29, 2013·5 cites·21 claims
- 0981US8112728B1Early timing estimation of timing statistical properties of placementHUTTON MICHAEL D·Filed 2009·Granted Feb 7, 2012·9 cites·19 claims
- 1075US8250505B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2009·Granted Aug 21, 2012·5 cites·17 claims
- 1175US7577929B1Early timing estimation of timing statistical properties of placementALTERA CORP·Filed 2005·Granted Aug 18, 2009·6 cites·26 claims
- 1271US7877721B2Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuitsALTERA CORP·Filed 2007·Granted Jan 25, 2011·4 cites·7 claims
- 1369US6167364AMethods and apparatus for automatically generating interconnect patterns in programmable logic devicesALTERA CORP·Filed 1998·Granted Dec 26, 2000·58 cites·19 claims
- 1468US7587688B1User-directed timing-driven synthesisALTERA CORP·Filed 2006·Granted Sep 8, 2009·4 cites·26 claims
- 1568US7358766B2Mask-programmable logic device with programmable portionsALTERA CORP·Filed 2006·Granted Apr 15, 2008·4 cites·40 claims
- 1667US7725856B1Method and apparatus for performing parallel slack computationALTERA CORP·Filed 2006·Granted May 25, 2010·4 cites·21 claims
- 1766US8589838B1M/A for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2012·Granted Nov 19, 2013·1 cites·24 claims
- 1865US7231337B1Using assignment decision diagrams with control nodes for sequential review during behavioral simulationALTERA CORP·Filed 2004·Granted Jun 12, 2007·10 cites·12 claims
- 1963US8001537B1Method and apparatus for compiling programmable logic device configurationsALTERA CORP·Filed 2005·Granted Aug 16, 2011·3 cites·25 claims
- 2060US8161469B1Method and apparatus for comparing programmable logic device configurationsIOTOV MIHAIL·Filed 2005·Granted Apr 17, 2012·4 cites·43 claims
- 2157US9122826B1Method and apparatus for performing compilation using multiple design flowsALTERA CORP·Filed 2013·Granted Sep 1, 2015·0 cites·24 claims
- 2253US8516504B1Method for adding device information by extending an application programming interfacePARK JIM·Filed 2003·Granted Aug 20, 2013·6 cites·15 claims
- 2351US7064580B2Mask-programmable logic device with programmable portionsALTERA CORP·Filed 2004·Granted Jun 20, 2006·5 cites·40 claims
- 2449US6697773B1Using assignment decision diagrams with control nodes for sequential review during behavioral simulationALTERA CORP·Filed 1999·Granted Feb 24, 2004·20 cites·24 claims
- 2544US6173245B1Programmable logic array device design using parameterized logic modulesALTERA CORP·Filed 1995·Granted Jan 9, 2001·17 cites·17 claims
- 2634US6961690B1Behaviorial digital simulation using hybrid control and data flow representationsALTERA CORP·Filed 1999·Granted Nov 1, 2005·8 cites·22 claims
- 2734US5768562AMethods for implementing logic in auxiliary components associated with programmable logic array devicesALTERA CORP·Filed 1995·Granted Jun 16, 1998·6 cites·15 claims
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