Inventor · disambiguated record
Robert E. Mains
Also filed as: MAINS ROBERT E · MAINS ROBERT EDWARD
12 granted patents·2 pending applications·227 citations·filing 1995–2013
92Inventor score
Top patents by PatentIndex Score
14 records- 0181US7802217B1Leakage power optimization considering gate input activity and timing slackORACLE AMERICA INC·Filed 2008·Granted Sep 21, 2010·12 cites·20 claims
- 0279US8732638B1Verifying proper representation of semiconductor device fingersORACLE INT CORP·Filed 2013·Granted May 20, 2014·10 cites·18 claims
- 0378US7797658B2Multithreaded static timing analysisORACLE AMERICA INC·Filed 2007·Granted Sep 14, 2010·9 cites·14 claims
- 0474US7206958B1Determining cycle adjustments for static timing analysis of multifrequency circuitsSUN MICROSYSTEMS INC·Filed 2003·Granted Apr 17, 2007·23 cites·39 claims
- 0570US7958474B2Highly threaded static timerORACLE AMERICA INC·Filed 2008·Granted Jun 7, 2011·7 cites·26 claims
- 0666US6014510AMethod for performing timing analysis of a clock circuitIBM·Filed 1996·Granted Jan 11, 2000·50 cites·27 claims
- 0762US7216316B1Method for evaluating nets in crosstalk noise analysisSUN MICROSYSTEMS INC·Filed 2004·Granted May 8, 2007·11 cites·17 claims
- 0860US6185723B1Method for performing timing analysis of a clock-shaping circuitIBM·Filed 1996·Granted Feb 6, 2001·37 cites·27 claims
- 0958US5946475AMethod for performing transistor-level static timing analysis of a logic circuitIBM·Filed 1997·Granted Aug 31, 1999·34 cites·19 claims
- 1053US5771375AAutomatic delay adjustment for static timing analysis using clock edge identification and half cycle pathsIBM·Filed 1995·Granted Jun 23, 1998·29 cites·22 claims
- 1151US7051305B1Delay estimation using edge specific miller capacitancesSUN MICROSYSTEMS INC·Filed 2004·Granted May 23, 2006·5 cites·17 claims
- 1242US8380656B2Technique for fast power estimation using probabilistic analysis of combinational logicORACLE AMERICA INC·Filed 2009·Granted Feb 19, 2013·0 cites·16 claims
- 1342US2005091555A1Abstraction generation for hierarchical timing analysis using implicity connectivity graph derived from domain propagationFiled 2003·Application pending·0 cites
- 1441US2005177357A1Static timing model for combinatorial gates having clock signal inputFiled 2004·Application pending·0 cites
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