Inventor · disambiguated record
Jean-Marc Masgonty
Also filed as: MASGONTY JEAN-MARC
9 granted patents·61 citations·filing 1995–2003
86Inventor score
Files withSUISSE ELECTRONIQUE MICROTECH9
Top patents by PatentIndex Score
9 records- 0161US5748522AMemory element of the master-slave flip-flop type, constructed by CMOS technologySUISSE ELECTRONIQUE MICROTECH·Filed 1996·Granted May 5, 1998·18 cites·25 claims
- 0257US6323710B1D-type master-slave flip-flopSUISSE ELECTRONIQUE MICROTECH·Filed 1999·Granted Nov 27, 2001·16 cites·20 claims
- 0353US7143072B2Method and a system for calculating the values of the neurons of a neural networkSUISSE ELECTRONIQUE MICROTECH·Filed 2002·Granted Nov 28, 2006·6 cites·17 claims
- 0441US6366504B1Random access memorySUISSE ELECTRONIQUE MICROTECH·Filed 2000·Granted Apr 2, 2002·4 cites·6 claims
- 0538US7213127B2System for producing addresses for a digital signal processorSUISSE ELECTRONIQUE MICROTECH·Filed 2003·Granted May 1, 2007·0 cites·22 claims
- 0635US5686856AMultiplexer of logic variablesSUISSE ELECTRONIQUE MICROTECH·Filed 1995·Granted Nov 11, 1997·4 cites·13 claims
- 0733US5845311AHierarchical ROMs that are selectively accessed by microprocessor instructions containing codesSUISSE ELECTRONIQUE MICROTECH·Filed 1996·Granted Dec 1, 1998·7 cites·12 claims
- 0829US6275928B1Microprocessor instruction pipeline having inhibit logic at each stageSUISSE ELECTRONIQUE MICROTECH·Filed 1996·Granted Aug 14, 2001·4 cites·5 claims
- 0928US6023739ASystem for information processing comprising plurality of processors where interconnection nodes insure priority access to corresponding addressable spaces and establish hierarchy of processor priority accessSUISSE ELECTRONIQUE MICROTECH·Filed 1997·Granted Feb 8, 2000·2 cites·7 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →