Inventor · disambiguated record
Phillip M. Jones
Also filed as: JONES PHILLIP M · JONES PHILLIP MATTHEW
39 granted patents·2 pending applications·1,660 citations·filing 1997–2012
98Inventor score
Files withCOMPAQ COMPUTER CORP22HEWLETT PACKARD DEVELOPMENT CO9COMPAQ INFORMATION TECHNOLOGIE4QUALCOMM INC3VENKUMAHANTI SURESH K1
Top patents by PatentIndex Score
41 records- 0194US6286083B1Computer system with adaptive memory arbitration schemeCOMPAQ COMPUTER CORP·Filed 1998·Granted Sep 4, 2001·213 cites·26 claims
- 0290US6865647B2Dynamic cache partitioningHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Mar 8, 2005·53 cites·18 claims
- 0390US6470429B1System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoopsCOMPAQ INFORMATION TECHNOLOGIE·Filed 2000·Granted Oct 22, 2002·66 cites·20 claims
- 0485US6078338AAccelerated graphics port programmable memory access arbiterCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 20, 2000·74 cites·32 claims
- 0584US6823409B2Coherency control module for maintaining cache coherency in a multi-processor-bus systemHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 23, 2004·42 cites·17 claims
- 0684US6356972B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Mar 12, 2002·34 cites·17 claims
- 0784US5999198AGraphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port deviceCOMPAQ COMPUTER CORP·Filed 1997·Granted Dec 7, 1999·73 cites·21 claims
- 0883US6848015B2Arbitration technique based on processor task priorityHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Jan 25, 2005·29 cites·28 claims
- 0983US6662272B2Dynamic cache partitioningHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 9, 2003·30 cites·18 claims
- 1083US6505260B2Computer system with adaptive memory arbitration schemeCOMPAQ INFORMATION TECHNOLOGIE·Filed 2001·Granted Jan 7, 2003·34 cites·54 claims
- 1183US5905509AAccelerated Graphics Port two level Gart cache having distributed first level cachesCOMPAQ COMPUTER CORP·Filed 1997·Granted May 18, 1999·116 cites·34 claims
- 1281US6463510B1Apparatus for identifying memory requests originating on remote I/O devices as noncacheableCOMPAQ INFORMATION TECHNOLOGIE·Filed 2000·Granted Oct 8, 2002·32 cites·20 claims
- 1379US7502895B2Techniques for reducing castouts in a snoop filterHEWLETT PACKARD DEVELOPMENT CO·Filed 2005·Granted Mar 10, 2009·9 cites·16 claims
- 1476US6160562ASystem and method for aligning an initial cache line of data read from local memory by an input/output deviceCOMPAQ COMPUTER CORP·Filed 1998·Granted Dec 12, 2000·73 cites·18 claims
- 1575US7827356B2System and method of using an N-way cacheQUALCOMM INC·Filed 2007·Granted Nov 2, 2010·6 cites·30 claims
- 1674US9122486B2Bimodal branch predictor encoded in a branch instructionVENKUMAHANTI SURESH K·Filed 2010·Granted Sep 1, 2015·5 cites·22 claims
- 1774US6202101B1System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefromCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 13, 2001·58 cites·10 claims
- 1873US6269433B1Memory controller using queue look-ahead to reduce memory latencyCOMPAQ COMPUTER CORP·Filed 1998·Granted Jul 31, 2001·65 cites·16 claims
- 1973US6247102B1Computer system employing memory controller and bridge interface permitting concurrent operationCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 12, 2001·68 cites·41 claims
- 2072US6829665B2Next snoop predictor in a host controllerHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Dec 7, 2004·17 cites·21 claims
- 2172US6272651B1System and method for improving processor read latency in a system employing error checking and correctionCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 7, 2001·61 cites·19 claims
- 2272US5999743ASystem and method for dynamically allocating accelerated graphics port memory spaceCOMPAQ COMPUTER CORP·Filed 1997·Granted Dec 7, 1999·42 cites·26 claims
- 2372US5949436AAccelerated graphics port multiple entry gart cache allocation system and methodCOMPAQ COMPUTER CORP·Filed 1997·Granted Sep 7, 1999·67 cites·24 claims
- 2472US5936640AAccelerated graphics port memory mapped status and control registersCOMPAQ COMPUTER CORP·Filed 1997·Granted Aug 10, 1999·64 cites·58 claims
- 2569US5986677AAccelerated graphics port read transaction mergingCOMPAQ COMPUTER CORP·Filed 1997·Granted Nov 16, 1999·57 cites·25 claims
- 2667US9804969B2Speculative addressing using a virtual address-to-physical address page crossing bufferQUALCOMM INC·Filed 2012·Granted Oct 31, 2017·2 cites·24 claims
- 2767US5914727AValid flag for disabling allocation of accelerated graphics port memory spaceCOMPAQ COMPUTER CORP·Filed 1997·Granted Jun 22, 1999·52 cites·27 claims
- 2866US7685411B2Multi-mode instruction memory unitQUALCOMM INC·Filed 2005·Granted Mar 23, 2010·3 cites·28 claims
- 2964US6279065B1Computer system with improved memory accessCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 21, 2001·43 cites·18 claims
- 3062US5990914AGenerating an error signal when accessing an invalid memory pageCOMPAQ COMPUTER CORP·Filed 1997·Granted Nov 23, 1999·42 cites·47 claims
- 3160US6272580B1Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration systemCOMPAQ COMPUTER CORP·Filed 1999·Granted Aug 7, 2001·37 cites·22 claims
- 3255US7120758B2Technique for improving processor performanceHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Oct 10, 2006·4 cites·26 claims
- 3351US6209052B1System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiterCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 27, 2001·23 cites·18 claims
- 3449US2005097256A1Arbitration technique based on processor task priorityHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Application pending·0 cites
- 3548US6961800B2Method for improving processor performanceHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Nov 1, 2005·2 cites·23 claims
- 3648US6233661B1Computer system with memory controller that hides the next cycle during the current cycleCOMPAQ COMPUTER CORP·Filed 1998·Granted May 15, 2001·20 cites·15 claims
- 3745US6249847B1Computer system with synchronous memory arbiter that permits asynchronous memory requestsCOMPAQ COMPUTER CORP·Filed 1998·Granted Jun 19, 2001·17 cites·13 claims
- 3843US6199118B1System and method for aligning an initial cache line of data read from an input/output device by a central processing unitCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 6, 2001·15 cites·18 claims
- 3940US6216190B1System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral busCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 10, 2001·12 cites·22 claims
- 4038US2003065860A1Internal control bus in a multiple processor/multiple bus systemFiled 2001·Application pending·0 cites
- 4137US8078818B2Method and system for migrating memory segmentsWALKER WILLIAM J·Filed 2005·Granted Dec 13, 2011·0 cites·18 claims
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