Inventor · disambiguated record
Ranganathan Nagarajan
Also filed as: NAGARAJAN RANGANATHAN
21 granted patents·4 pending applications·826 citations·filing 2000–2022
96Inventor score
Files withINST OF MICROELECTRONICS10AGENCY SCIENCE TECH & RES8GLOBALFOUNDRIES SG PTE LTD2VANGUARD INT SEMICONDUCTOR SINGAPORE PTE LTD2AGENCY FOR SCIENCE TECHNOLOLGY1
Top patents by PatentIndex Score
25 records- 0196US6846725B2Wafer-level package for micro-electro-mechanical systemsINST OF MICROELECTRONICS·Filed 2003·Granted Jan 25, 2005·238 cites·18 claims
- 0295US7326629B2Method of stacking thin substrates by transfer bondingAGENCY SCIENCE TECH & RES·Filed 2005·Granted Feb 5, 2008·105 cites·41 claims
- 0392US7294890B2Fully salicided (FUSA) MOSFET structureAGENCY SCIENCE TECH & RES·Filed 2005·Granted Nov 13, 2007·24 cites·20 claims
- 0491US6717812B1Apparatus and method for fluid-based cooling of heat-generating devicesINST OF MICROELECTRONICS·Filed 2003·Granted Apr 6, 2004·113 cites·19 claims
- 0588US7183176B2Method of forming through-wafer interconnects for vertical wafer level packagingAGENCY SCIENCE TECH & RES·Filed 2004·Granted Feb 27, 2007·57 cites·28 claims
- 0687US7230318B2RF and MMIC stackable micro-modulesAGENCY SCIENCE TECH & RES·Filed 2003·Granted Jun 12, 2007·48 cites·13 claims
- 0787US6461888B1Lateral polysilicon beam processINST OF MICROELECTRONICS·Filed 2001·Granted Oct 8, 2002·70 cites·27 claims
- 0886US11267696B2MEMS devices and methods of forming thereofVANGUARD INT SEMICONDUCTOR SINGAPORE PTE LTD·Filed 2019·Granted Mar 8, 2022·3 cites·9 claims
- 0982US6716570B2Low temperature resist trimming processINST OF MICROELECTRONICS·Filed 2002·Granted Apr 6, 2004·32 cites·30 claims
- 1080US6573154B1High aspect ratio trench isolation process for surface micromachined sensors and actuatorsINST OF MICROELECTRONICS·Filed 2000·Granted Jun 3, 2003·35 cites·20 claims
- 1179US6662654B2Z-axis accelerometerINST OF MICROELECTRONICS·Filed 2003·Granted Dec 16, 2003·21 cites·10 claims
- 1274US6571628B1Z-axis accelerometerINST OF MICROELECTRONICS·Filed 2000·Granted Jun 3, 2003·17 cites·10 claims
- 1373US6787456B1Wafer-level inter-connector formation methodAGENCY SCIENCE TECH & RES·Filed 2003·Granted Sep 7, 2004·21 cites·29 claims
- 1472US7682914B2Fully salicided (FUCA) MOSFET structureAGENCY FOR SCIENCE TECHNOLOLGY·Filed 2007·Granted Mar 23, 2010·6 cites·20 claims
- 1572US6551937B2Process for device using partial SOIINST OF MICROELECTRONICS·Filed 2001·Granted Apr 22, 2003·25 cites·21 claims
- 1671US11767217B2MEMS devices and methods of forming thereofVANGUARD INT SEMICONDUCTOR SINGAPORE PTE LTD·Filed 2022·Granted Sep 26, 2023·0 cites·9 claims
- 1769US9240362B2Layer arrangement and a wafer level package comprising the layer arrangementAGENCY SCIENCE TECH & RES·Filed 2013·Granted Jan 19, 2016·3 cites·20 claims
- 1867US7381629B2Method of forming through-wafer interconnects for vertical wafer level packagingAGENCY SCIENCE TECH & RES·Filed 2007·Granted Jun 3, 2008·3 cites·12 claims
- 1963US7592703B2RF and MMIC stackable micro-modulesAGENCY SCIENCE TECH & RES·Filed 2007·Granted Sep 22, 2009·2 cites·19 claims
- 2051US6858459B2Method of fabricating micro-mirror switching deviceINST OF MICROELECTRONICS·Filed 2002·Granted Feb 22, 2005·3 cites·27 claims
- 2151US2024235512A9Micro-electro-mechanical system device and piezoelectric composite stack thereofVANGUARD INT SEMICONDUCT CORP·Filed 2022·Application pending·0 cites
- 2242US2004178171A1Sloped trench etching processFiled 2004·Application pending·0 cites
- 2341US2015048509A1Cmos compatible wafer bonding layer and processGLOBALFOUNDRIES SG PTE LTD·Filed 2014·Application pending·0 cites
- 2440US2002166838A1Sloped trench etching processINST OF MICROELECTRONICS·Filed 2001·Application pending·0 cites
- 2539US11631800B2Piezoelectric MEMS devices and methods of forming thereofGLOBALFOUNDRIES SG PTE LTD·Filed 2019·Granted Apr 18, 2023·0 cites·20 claims
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