Inventor · disambiguated record
Ritu Shrivastava
Also filed as: SHRIVASTAVA RITU
25 granted patents·1 pending application·881 citations·filing 1987–2021
97Inventor score
Files withALLIANCE SEMICONDUCTOR CORP15ZETTACORE INC3ALLIANCE SEMICONDUCTOR1ALLIANCE SEMICONDUCTORS1ALLIANCE SEMICONDUCTORS CORP1
Top patents by PatentIndex Score
26 records- 0196US5557122ASemiconductor electrode having improved grain structure and oxide growth propertiesALLIANCE SEMICONDUCTORS CORP·Filed 1995·Granted Sep 17, 1996·364 cites·13 claims
- 0294US5518942AMethod of making flash EPROM cell having improved erase characteristics by using a tilt angle implantALLIANCE SEMICONDUCTOR CORP·Filed 1995·Granted May 21, 1996·109 cites·13 claims
- 0393US8395926B2Memory cell with resistance-switching layers and lateral arrangementKREUPL FRANZ·Filed 2011·Granted Mar 12, 2013·13 cites·22 claims
- 0490US5416738ASingle transistor flash EPROM cell and method of operationALLIANCE SEMICONDUCTOR CORP·Filed 1994·Granted May 16, 1995·78 cites·13 claims
- 0588US5994730ADRAM cell having storage capacitor contact self-aligned to bit lines and word linesALLIANCE SEMICONDUCTOR CORP·Filed 1996·Granted Nov 30, 1999·50 cites·14 claims
- 0687US7358113B2Processing systems and methods for molecular memoryZETTACORE INC·Filed 2005·Granted Apr 15, 2008·12 cites·6 claims
- 0786US4764248ARapid thermal nitridized oxide locos processCYPRESS SEMICONDUCTOR CORP·Filed 1987·Granted Aug 16, 1988·83 cites·8 claims
- 0876US7799598B2Processing systems and methods for molecular memoryZETTACORE INC·Filed 2008·Granted Sep 21, 2010·4 cites·19 claims
- 0967US6166409AFlash EPROM memory cell having increased capacitive couplingALLIANCE SEMICONDUCTOR CORP·Filed 1996·Granted Dec 26, 2000·23 cites·22 claims
- 1065US6258714B1Self-aligned contacts for salicided MOS devicesALLIANCE SEMICONDUCTOR CORP·Filed 1999·Granted Jul 10, 2001·24 cites·15 claims
- 1164US6429076B2Flash EPROM memory cell having increased capacitive coupling and method of manufacture thereofALLIANCE SEMICONDUCTOR CORP·Filed 2001·Granted Aug 6, 2002·10 cites·22 claims
- 1264US6373089B1DRAM cell having storage capacitor contact self-aligned to bit lines and word linesALLIANCE SEMICONDUCTOR CORP·Filed 2000·Granted Apr 16, 2002·7 cites·5 claims
- 1362US7642546B2Molecular memory devices including solid-state dielectric layers and related methodsZETTACORE INC·Filed 2006·Granted Jan 5, 2010·5 cites·43 claims
- 1461US6921688B2Method of and apparatus for integrating flash EPROM and SRAM cells on a common substrateALLIANCE SEMICONDUCTOR·Filed 2003·Granted Jul 26, 2005·8 cites·7 claims
- 1560US6133602AMethod of reducing dielectric damage due to charging in the fabrication of stacked gate structuresALLIANCE SEMICONDUCTOR CORP·Filed 1999·Granted Oct 17, 2000·14 cites·6 claims
- 1659US6472267B2DRAM cell having storage capacitor contact self-aligned to bit lines and word linesALLIANCE SEMICONDUCTOR CORP·Filed 2001·Granted Oct 29, 2002·5 cites·11 claims
- 1757US5856944ASelf-converging over-erase repair method for flash EPROMALLIANCE SEMICONDUCTOR CORP·Filed 1995·Granted Jan 5, 1999·18 cites·24 claims
- 1857US5701264ADynamic random access memory cell having increased capacitanceALLIANCE SEMICONDUCTOR CORP·Filed 1997·Granted Dec 23, 1997·17 cites·20 claims
- 1954US6392267B1Flash EPROM array with self-aligned source contacts and programmable sector erase architectureALLIANCE SEMICONDUCTOR CORP·Filed 1997·Granted May 21, 2002·15 cites·26 claims
- 2046US6589834B1Semiconductor chip that isolates DRAM cells from the peripheral circuitry and reduces the cell leakage currentALLIANCE SEMICONDUCTOR CORP·Filed 2001·Granted Jul 8, 2003·2 cites·3 claims
- 2143US6020237AMethod of reducing dielectric damage due to charging in the fabrication of stacked gate structuresALLIANCE SEMICONDUCTOR CORP·Filed 1998·Granted Feb 1, 2000·5 cites·29 claims
- 2240US6903434B2Method and apparatus for integrating flash EPROM and SRAM cells on a common substrateALLIANCE SEMICONDUCTORS·Filed 1999·Granted Jun 7, 2005·9 cites·15 claims
- 2338US11632365B2System and method for smart authenticationJPMORGAN CHASE BANK NA·Filed 2021·Granted Apr 18, 2023·0 cites·15 claims
- 2433US5731606AReliable edge cell array designFiled 1995·Granted Mar 24, 1998·3 cites·8 claims
- 2533US2002081802A1Interconnect to plate contact/via arrangement for random access memoryFiled 2001·Application pending·0 cites
- 2626US5672535AMethod of fabricating DRAM cell with self-aligned contactALLIANCE SEMICONDUCTOR CORP·Filed 1996·Granted Sep 30, 1997·3 cites·6 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →