Inventor · disambiguated record
Yuen H. Chan
Also filed as: CHAN YUEN · CHAN YUEN H · CHAN YUEN HUNG
84 granted patents·7 pending applications·1,068 citations·filing 1981–2019
99Inventor score
Top patents by PatentIndex Score
91 records- 0198US5481500APrecharged bit decoder and sense amplifier with integrated latch usable in pipelined memoriesIBM·Filed 1994·Granted Jan 2, 1996·437 cites·4 claims
- 0297US7376001B2Row circuit ring oscillator method for evaluating memory cell performanceIBM·Filed 2005·Granted May 20, 2008·81 cites·12 claims
- 0393US9742408B1Dynamic decode circuit with active glitch controlIBM·Filed 2016·Granted Aug 22, 2017·8 cites·15 claims
- 0491US9966958B2Dynamic decode circuit with active glitch controlIBM·Filed 2017·Granted May 8, 2018·8 cites·12 claims
- 0589US7483322B2Ring oscillator row circuit for evaluating memory cell performanceIBM·Filed 2007·Granted Jan 27, 2009·17 cites·10 claims
- 0689US7113433B2Local bit select with suppression of fast read before writeIBM·Filed 2005·Granted Sep 26, 2006·23 cites·2 claims
- 0786US6934182B2Method to improve cache capacity of SOI and bulkIBM·Filed 2003·Granted Aug 23, 2005·31 cites·11 claims
- 0885US10890623B1Power saving scannable latch output driverIBM·Filed 2019·Granted Jan 12, 2021·2 cites·20 claims
- 0981US10367507B2Dynamic decode circuit with active glitch controlIBM·Filed 2018·Granted Jul 30, 2019·3 cites·19 claims
- 1081US7142064B2SRAM ring oscillatorIBM·Filed 2004·Granted Nov 28, 2006·22 cites·4 claims
- 1181US4598390ARandom access memory RAM employing complementary transistor switch (CTS) memory cellsIBM·Filed 1984·Granted Jul 1, 1986·31 cites·23 claims
- 1280US7478297B2Merged MISR and output register without performance impact for circuits under testIBM·Filed 2007·Granted Jan 13, 2009·8 cites·4 claims
- 1380US7336546B2Global bit select circuit with dual read and write bit line pairsIBM·Filed 2005·Granted Feb 26, 2008·11 cites·1 claims
- 1480US6990038B1Clock driver and boundary latch for a multi-port SRAMIBM·Filed 2005·Granted Jan 24, 2006·13 cites·28 claims
- 1580US6868000B2Coupled body contacts for SOI differential circuitsIBM·Filed 2003·Granted Mar 15, 2005·27 cites·31 claims
- 1679US6788112B1High performance dual-stage sense amplifier circuitIBM·Filed 2003·Granted Sep 7, 2004·30 cites·25 claims
- 1776US7170774B2Global bit line restore timing scheme and circuitIBM·Filed 2005·Granted Jan 30, 2007·9 cites·20 claims
- 1875US7305602B2Merged MISR and output register without performance impact for circuits under testIBM·Filed 2005·Granted Dec 4, 2007·8 cites·19 claims
- 1975US7272030B2Global bit line restore timing scheme and circuitIBM·Filed 2006·Granted Sep 18, 2007·8 cites·12 claims
- 2073US7606060B2Eight transistor SRAM cell with improved stability requiring only one word lineIBM·Filed 2007·Granted Oct 20, 2009·7 cites·2 claims
- 2173US7295458B2Eight transistor SRAM cell with improved stability requiring only one word lineIBM·Filed 2006·Granted Nov 13, 2007·7 cites·11 claims
- 2273US7293209B2Split L2 latch with glitch free programmable delayIBM·Filed 2005·Granted Nov 6, 2007·7 cites·2 claims
- 2373US7167385B2Method and apparatus for controlling the timing of precharge in a content addressable memory systemIBM·Filed 2005·Granted Jan 23, 2007·9 cites·20 claims
- 2472US7936638B2Enhanced programmable pulsewidth modulating circuit for array clock generationIBM·Filed 2009·Granted May 3, 2011·6 cites·19 claims
- 2572US7787284B2Integrated circuit chip with improved array stabilityIBM·Filed 2008·Granted Aug 31, 2010·5 cites·20 claims
- 2672US7463537B2Global bit select circuit interface with dual read and write bit line pairsIBM·Filed 2007·Granted Dec 9, 2008·7 cites·1 claims
- 2771US5783949APrecharged bit decoder and sense amplifier with integrated latch usable in pipelined memoriesIBM·Filed 1995·Granted Jul 21, 1998·23 cites·7 claims
- 2870US7936198B2Progamable control clock circuit for arraysIBM·Filed 2008·Granted May 3, 2011·4 cites·16 claims
- 2969US6850460B1High performance programmable array local clock generatorIBM·Filed 2004·Granted Feb 1, 2005·17 cites·5 claims
- 3067US9070433B1SRAM supply voltage global bitline precharge pulseIBM·Filed 2014·Granted Jun 30, 2015·3 cites·20 claims
- 3166US5553029APrecharged bit decoder and sense amplifier with integrated latch usable in pipelined memoriesIBM·Filed 1995·Granted Sep 3, 1996·20 cites·9 claims
- 3262US9401698B1Transforming a phase-locked-loop generated chip clock signal to a local clock signalIBM·Filed 2015·Granted Jul 26, 2016·1 cites·17 claims
- 3361US8233331B2Single clock dynamic compare circuitCHAN YUEN H·Filed 2010·Granted Jul 31, 2012·2 cites·16 claims
- 3460US7173875B2SRAM array with improved cell stabilityIBM·Filed 2004·Granted Feb 6, 2007·10 cites·38 claims
- 3558US9792967B1Managing semiconductor memory array leakage currentIBM·Filed 2016·Granted Oct 17, 2017·1 cites·14 claims
- 3658US8587990B2Global bit line restore by most significant bit of an address lineCHAN YUEN H·Filed 2011·Granted Nov 19, 2013·2 cites·15 claims
- 3758US8299833B2Programmable control clock circuit including scan modeBUNCE PAUL A·Filed 2010·Granted Oct 30, 2012·2 cites·17 claims
- 3857US9786339B2Dual mode operation having power saving and active modes in a stacked circuit topology with logic preservationIBM·Filed 2016·Granted Oct 10, 2017·1 cites·18 claims
- 3956US9281024B2Write/read priority blocking scheme using parallel static address decode pathIBM·Filed 2014·Granted Mar 8, 2016·1 cites·8 claims
- 4055US7813189B2Array data input latch and data clocking schemeIBM·Filed 2008·Granted Oct 12, 2010·3 cites·20 claims
- 4155US5552745ASelf-resetting CMOS multiplexer with static output driverIBM·Filed 1994·Granted Sep 3, 1996·10 cites·16 claims
- 4254US5022010AWord decoder for a memory arrayIBM·Filed 1989·Granted Jun 4, 1991·13 cites·5 claims
- 4353US10312915B2Dynamic decode circuit with active glitch control methodIBM·Filed 2018·Granted Jun 4, 2019·0 cites·20 claims
- 4453US10312916B2Dynamic decode circuit with delayed prechargeIBM·Filed 2018·Granted Jun 4, 2019·0 cites·15 claims
- 4552US10320388B2Dynamic decode circuit with active glitch control methodIBM·Filed 2018·Granted Jun 11, 2019·0 cites·19 claims
- 4652US8237481B2Low power programmable clock delay generator with integrated decode functionCHAN YUEN H·Filed 2008·Granted Aug 7, 2012·2 cites·5 claims
- 4751US10224933B2Dynamic decode circuit with active glitch controlIBM·Filed 2017·Granted Mar 5, 2019·0 cites·16 claims
- 4851US8339893B2Dual beta ratio SRAMCHAN YUEN H·Filed 2009·Granted Dec 25, 2012·2 cites·4 claims
- 4950US7170799B2SRAM and dual single ended bit sense for an SRAMIBM·Filed 2005·Granted Jan 30, 2007·2 cites·26 claims
- 5049US8325543B2Global bit select circuit interface with false write through blockingCHAN YUEN HUNG·Filed 2010·Granted Dec 4, 2012·2 cites·20 claims
Showing the top 50 of 91 patent records by PatentIndex Score.
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