Inventor · disambiguated record
Matthew C. Merten
Also filed as: MERTEN MATTHEW · MERTEN MATTHEW C · MERTEN MATTHEW CARL · MERTEN MATTHEW T
58 granted patents·16 pending applications·323 citations·filing 2000–2023
98Inventor score
Top patents by PatentIndex Score
74 records- 0193US9465680B1Method and apparatus for processor performance monitoringINTEL CORP·Filed 2015·Granted Oct 11, 2016·17 cites·24 claims
- 0291US6681387B1Method and apparatus for instruction execution hot spot detection and monitoring in a data processing unitUNIV ILLINOIS·Filed 2000·Granted Jan 20, 2004·147 cites·59 claims
- 0390US10409612B2Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·7 cites·20 claims
- 0489US9606602B2Method and apparatus to prevent voltage droop in a computerINTEL CORP·Filed 2014·Granted Mar 28, 2017·13 cites·17 claims
- 0585US9965375B2Virtualizing precise event based samplingINTEL CORP·Filed 2016·Granted May 8, 2018·4 cites·28 claims
- 0684US7302557B1Method and apparatus for modulo scheduled loop execution in a processor architectureIMPACT TECHNOLOGIES INC·Filed 2000·Granted Nov 27, 2007·45 cites·29 claims
- 0781US10496522B2Virtualizing precise event based samplingINTEL CORP·Filed 2018·Granted Dec 3, 2019·2 cites·20 claims
- 0879US9182986B2Copy-on-write buffer for restoring program code from a speculative region to a non-speculative regionRAJWAR RAVI·Filed 2012·Granted Nov 10, 2015·7 cites·28 claims
- 0977US8438369B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2010·Granted May 7, 2013·4 cites·13 claims
- 1075US7529914B2Method and apparatus for speculative execution of uncontended lock instructionsINTEL CORP·Filed 2004·Granted May 5, 2009·19 cites·31 claims
- 1174US10216616B2Cooperative triggeringINTEL CORP·Filed 2016·Granted Feb 26, 2019·2 cites·26 claims
- 1272US11531542B2Addition instructions with independent carry chainsINTEL CORP·Filed 2021·Granted Dec 20, 2022·0 cites·18 claims
- 1372US11080045B2Addition instructions with independent carry chainsGOPAL VINODH·Filed 2011·Granted Aug 3, 2021·2 cites·16 claims
- 1471US11061807B2Trace management during aborted speculative operationsINTEL CORP·Filed 2018·Granted Jul 13, 2021·1 cites·17 claims
- 1571US9542191B2Hardware profiling mechanism to enable page level automatic binary translationCAPRIOLI PAUL·Filed 2012·Granted Jan 10, 2017·3 cites·20 claims
- 1671US7590784B2Detecting and resolving locks in a memory unitINTEL CORP·Filed 2006·Granted Sep 15, 2009·6 cites·12 claims
- 1770US8521993B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2007·Granted Aug 27, 2013·4 cites·4 claims
- 1868US9612938B2Providing status of a processing device with periodic synchronization point in instruction tracing systemINTEL CORP·Filed 2013·Granted Apr 4, 2017·2 cites·24 claims
- 1967US9442729B2Minimizing bandwidth to track return targets by an instruction tracing systemSTRONG BEEMAN C·Filed 2013·Granted Sep 13, 2016·2 cites·20 claims
- 2067US8095932B2Providing quality of service via thread priority in a hyper-threaded microprocessorMERTEN MATTHEW·Filed 2007·Granted Jan 10, 2012·6 cites·18 claims
- 2167US2022027154A1Addition instructions with independent carry chainsINTEL CORP·Filed 2021·Application pending·0 cites
- 2266US9746903B2Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuitINTEL CORP·Filed 2015·Granted Aug 29, 2017·1 cites·17 claims
- 2365US7516313B2Predicting contention in a processorINTEL CORP·Filed 2004·Granted Apr 7, 2009·10 cites·31 claims
- 2464US11055203B2Virtualizing precise event based samplingINTEL CORP·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 2563US9524191B2Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elementsMARDEN MORRIS·Filed 2010·Granted Dec 20, 2016·1 cites·12 claims
- 2663US9092214B2SIMD processor with programmable counters externally configured to count executed instructions having operands of particular register size and element size combinationKNAUTH LAURA A·Filed 2012·Granted Jul 28, 2015·2 cites·14 claims
- 2762US9292288B2Systems and methods for flag tracking in move elimination operationsKADGI VIJAYKUMAR B·Filed 2013·Granted Mar 22, 2016·2 cites·20 claims
- 2861US9535744B2Method and apparatus for continued retirement during commit of a speculative region of codeINTEL CORP·Filed 2013·Granted Jan 3, 2017·1 cites·21 claims
- 2961US7725696B1Method and apparatus for modulo scheduled loop execution in a processor architectureHWU WEN-MEI W·Filed 2007·Granted May 25, 2010·3 cites·28 claims
- 3060US10331452B2Tracking mode of a processing device in instruction tracing systemsINTEL CORP·Filed 2013·Granted Jun 25, 2019·1 cites·16 claims
- 3160US10261879B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Apr 16, 2019·0 cites·13 claims
- 3260US10210066B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Feb 19, 2019·0 cites·9 claims
- 3360US10152401B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Dec 11, 2018·0 cites·8 claims
- 3460US9354875B2Enhanced loop streaming detector to drive logic optimizationMERTEN MATTHEW C·Filed 2012·Granted May 31, 2016·2 cites·15 claims
- 3560US2006004585A1Supplier advisory management systemKIMBERLY CLARK CO·Filed 2004·Application pending·0 cites
- 3659US10248524B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Apr 2, 2019·0 cites·12 claims
- 3759US10223227B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Mar 5, 2019·0 cites·7 claims
- 3859US10210065B2Instruction and logic to test transactional execution statusINTEL CORP·Filed 2015·Granted Feb 19, 2019·0 cites·7 claims
- 3959US9372698B2Method and apparatus for implementing dynamic portbinding within a reservation stationINTEL CORP·Filed 2013·Granted Jun 21, 2016·1 cites·24 claims
- 4059US8402253B2Managing multiple threads in a single pipelineMERTEN MATTHEW·Filed 2006·Granted Mar 19, 2013·2 cites·18 claims
- 4159US7991965B2Technique for using memory attributesINTEL CORP·Filed 2006·Granted Aug 2, 2011·1 cites·35 claims
- 4258US9268596B2Instruction and logic to test transactional execution statusRAJWAR RAVI·Filed 2012·Granted Feb 23, 2016·0 cites·32 claims
- 4358US2023365228A1Pontoon Boat with Planing PanelsDJT 22 LLC·Filed 2023·Application pending·0 cites
- 4457US9753832B2Minimizing bandwith to compress output stream in instruction tracing systemsINTEL CORP·Filed 2013·Granted Sep 5, 2017·1 cites·24 claims
- 4557US9134788B2Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling current ramps in processing circuitSURYANARAYANAN ANUPAMA·Filed 2011·Granted Sep 15, 2015·1 cites·18 claims
- 4656US2017161106A1Providing thread fairness in a hyper-threaded microprocessorINTEL CORP·Filed 2016·Application pending·0 cites
- 4755US12189509B2Processor including monitoring circuitry for virtual countersINTEL CORP·Filed 2020·Granted Jan 7, 2025·0 cites·20 claims
- 4855US10261792B2Method and apparatus for obtaining a call stack to an event of interest and analyzing the sameINTEL CORP·Filed 2017·Granted Apr 16, 2019·0 cites·20 claims
- 4955US9733937B2Compare and exchange operation using sleep-wakeup mechanismINTEL CORP·Filed 2013·Granted Aug 15, 2017·0 cites·15 claims
- 5054US10409611B2Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·0 cites·20 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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