Inventor · disambiguated record
Prabhakar Kudva
Also filed as: KUDVA PRABHAKAR · KUDVA PRABHAKAR N · KUDVA PRABHAKAR NANDAVAR
36 granted patents·4 pending applications·1,108 citations·filing 1997–2022
98Inventor score
Top patents by PatentIndex Score
40 records- 0199US7723207B2Three dimensional integrated circuit and method of designIBM·Filed 2007·Granted May 25, 2010·277 cites·13 claims
- 0299US7312487B2Three dimensional integrated circuitIBM·Filed 2004·Granted Dec 25, 2007·335 cites·11 claims
- 0397US7421601B2Method and system for controlling power in a chip through a power-performance monitor and control unitIBM·Filed 2006·Granted Sep 2, 2008·73 cites·1 claims
- 0496US10467586B2Blockchain ledgers of material spectral signatures for supply chain integrity managementIBM·Filed 2017·Granted Nov 5, 2019·15 cites·11 claims
- 0593US8949101B2Hardware execution driven application level derating calculation for soft error rate analysisBOSE PRADIP·Filed 2011·Granted Feb 3, 2015·14 cites·25 claims
- 0690US10685323B2Blockchain ledgers of material spectral signatures for supply chain integrity managementIBM·Filed 2017·Granted Jun 16, 2020·6 cites·9 claims
- 0790US7065665B2Interlocked synchronous pipeline clock gatingIBM·Filed 2002·Granted Jun 20, 2006·45 cites·40 claims
- 0888US8112642B2Method and system for controlling power in a chip through a power-performance monitor and control unitBOSE PRADIP·Filed 2008·Granted Feb 7, 2012·14 cites·19 claims
- 0988US7880194B2Cross point switch using phase change materialIBM·Filed 2008·Granted Feb 1, 2011·16 cites·20 claims
- 1087US8639955B2Method and system for controlling power in a chip through a power performance monitor and control unitBOSE PRADIP·Filed 2011·Granted Jan 28, 2014·8 cites·24 claims
- 1187US7930578B2Method and system of peak power enforcement via autonomous token-based control and managementIBM·Filed 2007·Granted Apr 19, 2011·17 cites·16 claims
- 1287US7685457B2Interlocked synchronous pipeline clock gatingIBM·Filed 2007·Granted Mar 23, 2010·12 cites·34 claims
- 1387US6946869B2Method and structure for short range leakage control in pipelined circuitsIBM·Filed 2003·Granted Sep 20, 2005·31 cites·50 claims
- 1485US7308593B2Interlocked synchronous pipeline clock gatingIBM·Filed 2006·Granted Dec 11, 2007·10 cites·34 claims
- 1582US8073668B2Method and apparatus for testing a full system integrated circuit design by statistical fault injection using hardware-based simulationKELLINGTON JEFFREY WILLIAM·Filed 2008·Granted Dec 6, 2011·18 cites·21 claims
- 1681US7076681B2Processor with demand-driven clock throttling power reductionIBM·Filed 2002·Granted Jul 11, 2006·31 cites·31 claims
- 1777US7475227B2Method of stalling one or more stages in an interlocked synchronous pipelineIBM·Filed 2006·Granted Jan 6, 2009·5 cites·18 claims
- 1877US7047163B1Method and apparatus for applying fine-grained transforms during placement synthesis interactionIBM·Filed 2000·Granted May 16, 2006·25 cites·12 claims
- 1975US8091050B2Modeling system-level effects of soft errorsBOSE PRADIP·Filed 2008·Granted Jan 3, 2012·7 cites·20 claims
- 2073US11195145B2Blockchain ledgers of material spectral signatures for supply chain integrity managementIBM·Filed 2019·Granted Dec 7, 2021·1 cites·20 claims
- 2173US9811624B2Timing closure methodology including placement with initial delay valuesSYNOPSYS INC·Filed 2013·Granted Nov 7, 2017·2 cites·9 claims
- 2273US7178120B2Method for performing timing closure on VLSI chips in a distributed environmentIBM·Filed 2003·Granted Feb 13, 2007·19 cites·17 claims
- 2370US7100144B2System and method for topology selection to minimize leakage power during synthesisIBM·Filed 2003·Granted Aug 29, 2006·14 cites·34 claims
- 2468US9569582B2Template matching for resilience and security characteristics of sub-component chip designsIBM·Filed 2014·Granted Feb 14, 2017·2 cites·20 claims
- 2568US8832707B2Tunable error resilience computingHENDERSON DANIEL J·Filed 2009·Granted Sep 9, 2014·6 cites·15 claims
- 2668US6090153AMulti-threshold-voltage differential cascode voltage switch (DCVS) circuitsIBM·Filed 1997·Granted Jul 18, 2000·52 cites·19 claims
- 2766US8555234B2Verification of soft error resilienceTREMAINE ROBERT BRETT·Filed 2009·Granted Oct 8, 2013·5 cites·20 claims
- 2865US7801835B2Method for constructing autonomic advisors and learning procedural knowledge from scored examplesIBM·Filed 2005·Granted Sep 21, 2010·6 cites·20 claims
- 2963US6512397B1Circuit structures and methods for high-speed low-power select arbitrationIBM·Filed 2001·Granted Jan 28, 2003·12 cites·25 claims
- 3062US11934401B2Scalable count based interpretability for database artificial intelligence (AI)IBM·Filed 2022·Granted Mar 19, 2024·0 cites·20 claims
- 3159US7676779B2Logic block timing estimation using conesizeIBM·Filed 2007·Granted Mar 9, 2010·2 cites·16 claims
- 3257US7373615B2Method for optimization of logic circuits for routabilityIBM·Filed 2004·Granted May 13, 2008·5 cites·19 claims
- 3356US6608771B2Low-power circuit structures and methods for content addressable memories and random access memoriesIBM·Filed 2001·Granted Aug 19, 2003·9 cites·21 claims
- 3454US2008042140A1Three dimensional integrated circuit and method of designIBM·Filed 2007·Application pending·0 cites
- 3553US11557033B2Bacteria classificationIBM·Filed 2019·Granted Jan 17, 2023·0 cites·12 claims
- 3648US8621403B2Timing closure methodology including placement with initial delay valuesVAN GINNEKEN LUKAS P P P·Filed 2004·Granted Dec 31, 2013·2 cites·5 claims
- 3746US2008263325A1System and structure for synchronized thread priority selection in a deeply pipelined multithreaded microprocessorIBM·Filed 2007·Application pending·0 cites
- 3845US2008195984A1Method for optimization of logic circuits for routability improvementDOUGHERTY WILLIAM E·Filed 2008·Application pending·0 cites
- 3942US2009070720A1System to Identify Timing Differences from Logic Block Changes and Associated MethodsIBM·Filed 2007·Application pending·0 cites
- 4040US6314547B1Method for improving the assignment of circuit locations during fabricationIBM·Filed 1998·Granted Nov 6, 2001·12 cites·10 claims
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