Inventor · disambiguated record
Joel Roger Davidson
Also filed as: DAVIDSON JOEL R · DAVIDSON JOEL ROGER
17 granted patents·657 citations·filing 1987–2001
95Inventor score
Top patents by PatentIndex Score
17 records- 0187US6574727B1Method and apparatus for instruction sampling for performance monitoring and debugIBM·Filed 1999·Granted Jun 3, 2003·136 cites·31 claims
- 0284US6446029B1Method and system for providing temporal threshold support during performance monitoring of a pipelined processorIBM·Filed 1999·Granted Sep 3, 2002·123 cites·29 claims
- 0375US5613157AAddress range extension for a modular computerIBM·Filed 1996·Granted Mar 18, 1997·80 cites·13 claims
- 0472US6718403B2Hierarchical selection of direct and indirect counting events in a performance monitor unitIBM·Filed 2000·Granted Apr 6, 2004·19 cites·20 claims
- 0571US6725307B1Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor systemIBM·Filed 1999·Granted Apr 20, 2004·59 cites·16 claims
- 0671US6539502B1Method and apparatus for identifying instructions for performance monitoring in a microprocessorIBM·Filed 1999·Granted Mar 25, 2003·60 cites·28 claims
- 0768US6804692B2Method and apparatus for reassembly of data blocks within a network processorAGERE SYSTEMS INC·Filed 2001·Granted Oct 12, 2004·14 cites·25 claims
- 0863US6915480B2Processor with packet data flushing featureAGERE SYSTEMS INC·Filed 2001·Granted Jul 5, 2005·12 cites·20 claims
- 0960US7079539B2Method and apparatus for classification of packet data prior to storage in processor buffer memoryAGERE SYSTEMS INC·Filed 2001·Granted Jul 18, 2006·7 cites·17 claims
- 1059US4816805AResidue number system shift accumulator decoderGRUMMAN AEROSPACE CORP·Filed 1987·Granted Mar 28, 1989·13 cites·14 claims
- 1156US6530042B1Method and apparatus for monitoring the performance of internal queues in a microprocessorIBM·Filed 1999·Granted Mar 4, 2003·30 cites·39 claims
- 1255US6415378B1Method and system for tracking the progress of an instruction in an out-of-order processorIBM·Filed 1999·Granted Jul 2, 2002·30 cites·32 claims
- 1355US5619158AHierarchical clocking system using adaptive feedbackIBM·Filed 1995·Granted Apr 8, 1997·33 cites·8 claims
- 1448US6550002B1Method and system for detecting a flush of an instruction without a flush indicatorIBM·Filed 1999·Granted Apr 15, 2003·25 cites·26 claims
- 1546US8782287B2Methods and apparatus for using multiple reassembly memories for performing multiple functionsBOUCHARD GREGG A·Filed 2001·Granted Jul 15, 2014·1 cites·20 claims
- 1643US6629170B1Method and apparatus for a byte lane selectable performance monitor busIBM·Filed 1999·Granted Sep 30, 2003·15 cites·20 claims
- 1741US7113518B2Processor with reduced memory requirements for high-speed routing and switching of packetsAGERE SYSTEMS INC·Filed 2001·Granted Sep 26, 2006·0 cites·21 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →