Inventor · disambiguated record
Masaru Takehara
Also filed as: TAKEHARA MASARU
9 granted patents·3 pending applications·490 citations·filing 1994–2017
90Inventor score
Top patents by PatentIndex Score
12 records- 0197US6125424AMethod of writing, erasing, and controlling memory and memory device having erasing and moving componentsFUJITSU LTD·Filed 1998·Granted Sep 26, 2000·148 cites·29 claims
- 0297US5802551AMethod and apparatus for controlling the writing and erasing of information in a memory deviceFUJITSU LTD·Filed 1994·Granted Sep 1, 1998·200 cites·12 claims
- 0392US6766409B2Method of writing, erasing, and controlling memory for memory deviceFUJITSU LTD·Filed 2003·Granted Jul 20, 2004·43 cites·4 claims
- 0490US5983312ASimultaneously writing to and erasing two commonly numbered sectorsFUJITSU LTD·Filed 1997·Granted Nov 9, 1999·53 cites·4 claims
- 0587US6161163AMethod of writing, erasing, and controlling memory for memory deviceFUJITSU LTD·Filed 1999·Granted Dec 12, 2000·42 cites·3 claims
- 0662US7882279B2Bidirectional control circuitFUJITSU LTD·Filed 2009·Granted Feb 1, 2011·4 cites·10 claims
- 0744US9141465B2Reception circuit, information processing apparatus, and control methodFUJITSU LTD·Filed 2013·Granted Sep 22, 2015·0 cites·6 claims
- 0843US2013318390A1Information processing apparatus, method of measuring delay difference, and computer readable recording medium recorded with delay difference measuring programFUJITSU LTD·Filed 2013·Application pending·0 cites
- 0940US8539306B2Data processing circuit and data processing methodTAKEHARA MASARU·Filed 2011·Granted Sep 17, 2013·0 cites·9 claims
- 1040US2018046539A1Error detection code generating device and error detecting deviceFUJITSU LTD·Filed 2017·Application pending·0 cites
- 1137US2015171869A1Circuit and method of controlling a circuitFUJITSU LTD·Filed 2014·Application pending·0 cites
- 1230US8619930B2Synchronization circuit and synchronization methodTAKEHARA MASARU·Filed 2012·Granted Dec 31, 2013·0 cites·7 claims
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