Inventor

BASKER VEERARAGHAVAN S

US446 patents

⚠️ This page may combine multiple inventors who share the name “BASKER VEERARAGHAVAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BASKER VEERARAGHAVAN S

IBM

Recessed metal liner contact with copper fill

Replacement metal gate structures

Air-gap top spacer and self-aligned metal gate for vertical fets

Airgap formation between source/drain contacts and gates

Method and structure for forming gate contact above active area with trench silicide

Stacked nanowire field effect transistor

High-K/metal gate CMOS finFET with improved pFET threshold voltage

Replacement metal gate structures

Self-aligned gate isolation with asymmetric cut placement

Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)

Interlayer via

Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET)

Vertical transistor with a body contact for back-biasing

FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure

Forming metal-insulator-metal capacitor

Asymmetric multi-gate finFET

Semiconductor device including self-aligned gate structure and improved gate spacer topography

Forming strained and relaxed silicon and silicon germanium fins on the same wafer

Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains

Replacement metal gate structures

Replacement metal gate structures

Replacement metal gate structures

Replacement metal gate structures

Replacement metal gate structures

Precise control of vertical transistor gate length

Split fin field effect transistor enabling back bias on fin type field effect transistors

Electrical fuse and/or resistor structures

Electrical fuse and/or resistor structures

Replacement metal gate structures

FinFET devices

FinFET devices

Self aligned epitaxial based punch through control

Gate stack integrated metal resistors

Method and structure for forming gate contact above active area with trench silicide

Nanowire semiconductor device including lateral-etch barrier region

Structure and method to form liner silicide with improved contact resistance and reliablity

Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs

Independent gate vertical FinFET structure

Dual epitaxial process including spacer adjustment

FinFET with reduced capacitance

Strained silicon nFET and silicon germanium pFET on same wafer

Preventing Fin erosion and limiting EPI overburden in FinFET structures by composite hardmask

Preventing FIN erosion and limiting Epi overburden in FinFET structures by composite hardmask

finFET eDRAM strap connection structure

BASKER VEERARAGHAVAN S

Cut-very-last dual-epi flow

SOI FinFET with recessed merged Fins and liner for enhanced stress coupling

Finfet with reduced parasitic capacitance

High-K/metal gate CMOS finFET with improved pFET threshold voltage

FinFET spacer formation by oriented implantation

GLOBALFOUNDRIES US 2 LLC

Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides