Inventor

KHAKIFIROOZ ALI

US759 patents

⚠️ This page may combine multiple inventors who share the name “KHAKIFIROOZ ALI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KHAKIFIROOZ ALI

IBM

Gate-all-around nanowire MOSFET and method of formation

Contact formation to 3D monolithic stacked FinFETs

Method and structure of forming controllable unmerged epitaxial material

Dual work function integration for stacked FinFET

Self-aligned contacts for vertical field effect transistors

Method and structure for improving finFET with epitaxy source/drain

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

Gate-all-around nanowire MOSFET and method of formation

Dense finFET SRAM

Doping of FinFET structures

High-K/metal gate CMOS finFET with improved pFET threshold voltage

Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET)

Heterogeneous source drain region and extension region

Method to form stacked germanium nanowires and stacked III-V nanowires

Nanowire device with improved epitaxy

Nanowire transistor structures with merged source/drain regions using auxiliary pillars

FinFET structures having silicon germanium and silicon channels

Forming strained and relaxed silicon and silicon germanium fins on the same wafer

Strained SiGe nanowire having (111)-oriented sidewalls

Electrical fuse and/or resistor structures

Electrical fuse and/or resistor structures

Replacement low-k spacer

Dual work function integration for stacked FinFET

Distributed decoupling capacitor

Structure and method to form liner silicide with improved contact resistance and reliablity

Semiconductor structure with an L-shaped bottom plate

Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon

Structure and method to increase contact area in unmerged EPI integration for CMOS FinFETs

Fin cut on SIT level

Thin-film gallium nitride structures grown on graphene

FinFET with reduced capacitance

FinFET structures having silicon germanium and silicon fins

Semiconductor substrate with multiple SiGe regions having different germanium concentrations by a single epitaxy process

Fin isolation in multi-gate field effect transistors

Method and structure for forming a localized SOI finFET

FinFET and method of fabrication

Inverted thin channel mosfet with self-aligned expanded source/drain

Method of co-integration of strained-Si and relaxed Si or strained SiGe FETs on insulator with planar and non-planar architectures

Integrated circuit having raised source drains devices with reduced silicide contact resistance and methods to fabricate same

GLOBALFOUNDRIES INC

Methods of removing dummy fin structures when forming finFET devices

Methods of forming fin isolation regions on finFET semiconductor devices using an oxidation-blocking layer of material

Methods of forming isolation material on FinFET semiconductor devices and the resulting devices

Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same

INTEL CORP

Resuming storage die programming after power loss

Coarse pass and fine pass multi-level NVM programming

BEDELL STEPHEN W

Strained CMOS device, circuit and method of fabrication

XIE RUILONG

Methods of forming semiconductor devices with self-aligned contacts and low-k spacers and the resulting devices

ADAM THOMAS N

Semiconductor structure having a source and a drain with reverse facets

BASKER VEERARAGHAVAN S

High-K/metal gate CMOS finFET with improved pFET threshold voltage