Inventor · disambiguated record
Jyotirmoy Saikia
Also filed as: SAIKIA JYOTIRMOY
9 granted patents·1 pending application·46 citations·filing 2008–2017
83Inventor score
Technology areasG01R
Top patents by PatentIndex Score
10 records- 0187US8065651B2Implementing hierarchical design-for-test logic for modular circuit designKAPUR ROHIT·Filed 2009·Granted Nov 22, 2011·24 cites·21 claims
- 0286US8479067B2Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitryCHANDRA ANSHUMAN·Filed 2010·Granted Jul 2, 2013·12 cites·25 claims
- 0370US8584073B2Test design optimizer for configurable scan architecturesKAPUR ROHIT·Filed 2008·Granted Nov 12, 2013·7 cites·41 claims
- 0468US8954918B2Test design optimizer for configurable scan architecturesSYNOPSYS INC·Filed 2013·Granted Feb 10, 2015·2 cites·24 claims
- 0557US10203370B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2017·Granted Feb 12, 2019·0 cites·15 claims
- 0657US8521464B2Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimizationKUMAR ASHWIN·Filed 2010·Granted Aug 27, 2013·1 cites·20 claims
- 0756US9588179B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2014·Granted Mar 7, 2017·0 cites·20 claims
- 0853US9417287B2Scheme for masking output of scan chains in test circuitSYNOPSYS INC·Filed 2014·Granted Aug 16, 2016·0 cites·20 claims
- 0953US2016341795A1Scheme for Masking Output of Scan Chains in Test CircuitSYNOPSYS INC·Filed 2016·Application pending·0 cites
- 1048US10067187B2Handling of undesirable distribution of unknown values in testing of circuit using automated test equipmentSYNOPSYS INC·Filed 2014·Granted Sep 4, 2018·0 cites·19 claims
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