Inventor · disambiguated record
Viswanath Mohan
Also filed as: MOHAN VISWANATH
4 granted patents·12 citations·filing 2014–2023
64Inventor score
Technology areasG06F
Top patents by PatentIndex Score
4 records- 0188US9842055B2Address translation cache that supports simultaneous invalidation of common context entriesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Dec 12, 2017·12 cites·20 claims
- 0261US12367032B1Hot loadable programmable state machineADVANCED MICRO DEVICES INC·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 0356US9727480B2Efficient address translation caching in a processor that supports a large number of different address spacesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Aug 8, 2017·0 cites·20 claims
- 0435US10078597B2System and method of distinguishing system management mode entries in a translation address cache of a processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Sep 18, 2018·0 cites·24 claims
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