Inventor · disambiguated record
Shoji Sawamura
Also filed as: SAWAMURA SHOJI
9 granted patents·4 pending applications·5 citations·filing 2005–2022
79Inventor score
Top patents by PatentIndex Score
13 records- 0176US11868285B2Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from sourceKIOXIA CORP·Filed 2022·Granted Jan 9, 2024·0 cites·10 claims
- 0275US10929315B2Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from sourceTOSHIBA MEMORY CORP·Filed 2018·Granted Feb 23, 2021·2 cites·20 claims
- 0370US11537536B2Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from sourceKIOXIA CORP·Filed 2021·Granted Dec 27, 2022·0 cites·20 claims
- 0464US10459846B2Memory system which uses a host memoryTOSHIBA MEMORY CORP·Filed 2016·Granted Oct 29, 2019·1 cites·18 claims
- 0561US7627771B2Clock control hierarchy for integrated microprocessors and systems-on-a-chipIBM·Filed 2005·Granted Dec 1, 2009·2 cites·20 claims
- 0656US10042786B2Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from sourceTOSHIBA MEMORY CORP·Filed 2015·Granted Aug 7, 2018·0 cites·15 claims
- 0747US9354818B2Memory device and data storing methodTOSHIBA KK·Filed 2014·Granted May 31, 2016·0 cites·16 claims
- 0845US9575887B2Memory device, information-processing device and information-processing methodTOSHIBA KK·Filed 2014·Granted Feb 21, 2017·0 cites·20 claims
- 0940US2009222251A1Structure For An Integrated Circuit That Employs Multiple InterfacesIBM·Filed 2008·Application pending·0 cites
- 1037US2008147901A1Method and apparatus for interfacing to an integrated circuit that employs multiple interfacesIBM·Filed 2006·Application pending·0 cites
- 1135US9864548B2Memory module, electronic device and methodTOSHIBA MEMORY CORP·Filed 2016·Granted Jan 9, 2018·0 cites·15 claims
- 1235US2007092048A1RUNN counter phase controlCHELSTROM NATHAN P·Filed 2005·Application pending·0 cites
- 1335US2015058532A1Memory device, information-processing device and information-processing methodTOSHIBA KK·Filed 2013·Application pending·0 cites
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