Inventor · disambiguated record
Charles L. Johnson
Also filed as: JOHNSON CHARLES · JOHNSON CHARLES L · JOHNSON CHARLES LUTHER
22 granted patents·2 pending applications·679 citations·filing 1982–2015
96Inventor score
Top patents by PatentIndex Score
24 records- 0198US8736068B2Hybrid bonding techniques for multi-layer semiconductor stacksBARTLEY GERALD K·Filed 2012·Granted May 27, 2014·215 cites·11 claims
- 0295US9495498B2Universal inter-layer interconnect for multi-layer semiconductor stacksBARTLEY GERALD K·Filed 2012·Granted Nov 15, 2016·19 cites·16 claims
- 0392US8445918B2Thermal enhancement for multi-layer semiconductor stacksBARTLEY GERALD K·Filed 2010·Granted May 21, 2013·17 cites·18 claims
- 0491US8293578B2Hybrid bonding techniques for multi-layer semiconductor stacksBARTLEY GERALD K·Filed 2010·Granted Oct 23, 2012·11 cites·10 claims
- 0591US4939389AVLSI performance compensation for off-chip drivers and clock generationIBM·Filed 1988·Granted Jul 3, 1990·72 cites·46 claims
- 0690US9245813B2Horizontally aligned graphite nanofibers in etched silicon wafer troughs for enhanced thermal performanceIBM·Filed 2013·Granted Jan 26, 2016·13 cites·13 claims
- 0790US5077676AReducing clock skew in large-scale integrated circuitsIBM·Filed 1990·Granted Dec 31, 1991·67 cites·11 claims
- 0886US8140297B2Three dimensional chip fabricationBARTLEY GERALD K·Filed 2009·Granted Mar 20, 2012·12 cites·20 claims
- 0985US4857765ANoise control in an integrated circuit chipIBM·Filed 1989·Granted Aug 15, 1989·37 cites·3 claims
- 1081US9111899B2Horizontally and vertically aligned graphite nanofibers thermal interface material for use in chip stacksBARTLEY GERALD K·Filed 2012·Granted Aug 18, 2015·5 cites·13 claims
- 1179US8367478B2Method and system for internal layer-layer thermal enhancementIBM·Filed 2011·Granted Feb 5, 2013·5 cites·20 claims
- 1273US8330489B2Universal inter-layer interconnect for multi-layer semiconductor stacksBARTLEY GERALD K·Filed 2009·Granted Dec 11, 2012·4 cites·22 claims
- 1370US9817612B2High-performance hash joins using memory with extensive internal parallelismIBM·Filed 2014·Granted Nov 14, 2017·2 cites·12 claims
- 1470US5790838APipelined memory interface and method for using the sameIBM·Filed 1996·Granted Aug 4, 1998·30 cites·19 claims
- 1570US4495377ASubstrate wiring patterns for connecting to integrated-circuit chipsIBM·Filed 1982·Granted Jan 22, 1985·32 cites·16 claims
- 1668US8127079B2Intelligent cache injectionHEIL TIMOTHY H·Filed 2009·Granted Feb 28, 2012·4 cites·8 claims
- 1766US9811287B2High-performance hash joins using memory with extensive internal parallelismIBM·Filed 2015·Granted Nov 7, 2017·1 cites·6 claims
- 1864US5371764AMethod and apparatus for providing an uninterrupted clock signal in a data processing systemIBM·Filed 1992·Granted Dec 6, 1994·43 cites·11 claims
- 1957US5235521AReducing clock skew in large-scale integrated circuitsIBM·Filed 1991·Granted Aug 10, 1993·32 cites·12 claims
- 2055US5911063AMethod and apparatus for single phase clock distribution with minimal clock skewIBM·Filed 1997·Granted Jun 8, 1999·29 cites·12 claims
- 2151US2013011968A1Hybrid bonding techniques for multi-layer semiconductor stacksIBM·Filed 2012·Application pending·0 cites
- 2250US2012198406A1Universal inter-layer interconnect for multi-layer semiconductor stacksBARTLEY GERALD K·Filed 2012·Application pending·0 cites
- 2346US6260164B1SRAM that can be clocked on either clock phaseIBM·Filed 1998·Granted Jul 10, 2001·10 cites·13 claims
- 2446US5815694AApparatus and method to change a processor clock frequencyIBM·Filed 1995·Granted Sep 29, 1998·19 cites·17 claims
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