Inventor · disambiguated record
Michael A. Mendicino
Also filed as: MENDICINO MICHAEL A
11 granted patents·4 pending applications·356 citations·filing 1995–2008
91Inventor score
Top patents by PatentIndex Score
15 records- 0192US5633036ASelective low temperature chemical vapor deposition of titanium disilicide onto silicon regionsUNIV ILLINOIS·Filed 1995·Granted May 27, 1997·133 cites·12 claims
- 0290US6838332B1Method for forming a semiconductor device having electrical contact from opposite sidesFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Jan 4, 2005·45 cites·14 claims
- 0387US6724048B2Body-tied silicon on insulator semiconductor device and method thereforMOTOROLA INC·Filed 2003·Granted Apr 20, 2004·38 cites·5 claims
- 0485US6620656B2Method of forming body-tied silicon on insulator semiconductor deviceMOTOROLA INC·Filed 2001·Granted Sep 16, 2003·34 cites·18 claims
- 0584US6921961B2Semiconductor device having electrical contact from opposite sides including a via with an end formed at a bottom surface of the diffusion regionFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jul 26, 2005·28 cites·11 claims
- 0679US6271143B1Method for preventing trench fill erosionMOTOROLA INC·Filed 1999·Granted Aug 7, 2001·59 cites·25 claims
- 0778US7122421B2Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive elementFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Oct 17, 2006·6 cites·8 claims
- 0865US7161199B2Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 9, 2007·12 cites·26 claims
- 0956US8440539B2Isolation trench processing for strain controlSADAKA MARIAM G·Filed 2007·Granted May 14, 2013·1 cites·18 claims
- 1051US7573101B2Embedded substrate interconnect for underside contact to source and drain regionsFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Aug 11, 2009·0 cites·20 claims
- 1148US7345344B2Embedded substrate interconnect for underside contact to source and drain regionsFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 18, 2008·0 cites·20 claims
- 1244US2006194384A1Semiconductor device with multiple semiconductor layersFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 1338US2007184600A1Stressed-channel CMOS transistorsFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 1437US2005275018A1Semiconductor device with multiple semiconductor layersVENKATESAN SURESH·Filed 2004·Application pending·0 cites
- 1536US2006043500A1Transistor structure with stress modification and capacitive reduction feature in a channel direction and method thereofCHEN JIAN·Filed 2004·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →