Inventor · disambiguated record
Karl-Peter Pfefferl
Also filed as: PFEFFERL KARL-PETER
10 granted patents·1 pending application·185 citations·filing 1997–2007
90Inventor score
Technology areasG11C
Top patents by PatentIndex Score
11 records- 0188US6560134B2Memory configuration with a central connection areaINFINEON TECHNOLOGIES AG·Filed 2001·Granted May 6, 2003·52 cites·14 claims
- 0274US6310793B1Segmented word line architecture for dividing up a word line into a plurality of banks for cell arrays having long bit linesINFINEON TECHNOLOGIES AG·Filed 2000·Granted Oct 30, 2001·23 cites·4 claims
- 0368US5978931AVariable domain redundancy replacement configuration for a memory deviceIBM·Filed 1997·Granted Nov 2, 1999·29 cites·26 claims
- 0466US6078534ASemiconductor memory having redundancy circuitSIEMENS AG·Filed 1997·Granted Jun 20, 2000·26 cites·14 claims
- 0563US5970000ARepairable semiconductor integrated circuit memory by selective assignment of groups of redundancy elements to domainsIBM·Filed 1998·Granted Oct 19, 1999·22 cites·32 claims
- 0655US5881003AMethod of making a memory device fault tolerant using a variable domain redundancy replacement configurationIBM·Filed 1997·Granted Mar 9, 1999·17 cites·26 claims
- 0743US6138214ASynchronous dynamic random access memory architecture for sequential burst modeSIEMENS AG·Filed 1997·Granted Oct 24, 2000·9 cites·8 claims
- 0841US6295236B1Semiconductor memory of the random access type with a bus system organized in two planesINFINEON TECHNOLOGIES AG·Filed 2000·Granted Sep 25, 2001·3 cites·9 claims
- 0935US6654271B2Method for reading and storing binary memory cells signals and circuit arrangementINFINEON TECHNOLOGIES AG·Filed 2002·Granted Nov 25, 2003·1 cites·30 claims
- 1035US6226219B1Semiconductor memory with a plurality of memory banksINFINEON TECHNOLOGIES AG·Filed 2000·Granted May 1, 2001·3 cites·7 claims
- 1134US2007262791A1Integrated Circuit to Store a DatumQIMONDA AG·Filed 2007·Application pending·0 cites
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