Inventor · disambiguated record
Paul Rodman
Also filed as: RODMAN PAUL · RODMAN PAUL K · RODMAN PAUL KINGSLEY
30 granted patents·2 pending applications·1,840 citations·filing 1984–2022
98Inventor score
Files withRESHAPE INC9PRIME COMPUTER INC5MAGMA DESIGN AUTOMATION INC4SILICON GRAPHICS INC4DIGITAL EQUIPMENT CORP2
Top patents by PatentIndex Score
32 records- 0194US4833599AHierarchical priority branch handling for parallel execution in a parallel processorMULTIFLOW COMPUTER INC·Filed 1987·Granted May 23, 1989·233 cites·9 claims
- 0291US6557153B1Method and system for implementing a user interface for performing physical design operations on an integrated circuit netlistRESHAPE INC·Filed 2000·Granted Apr 29, 2003·62 cites·13 claims
- 0390US6691221B2Loading previously dispatched slots in multiple instruction dispatch buffer before dispatching remaining slots for parallel executionMIPS TECH INC·Filed 2001·Granted Feb 10, 2004·52 cites·39 claims
- 0490US5179680AInstruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatusDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jan 12, 1993·155 cites·3 claims
- 0590US4761755AData processing system and method having an improved arithmetic unitPRIME COMPUTER INC·Filed 1984·Granted Aug 2, 1988·117 cites·9 claims
- 0689US6553554B1Method and system for implementing a graphical user interface for depicting loose fly line interconnections between multiple blocks of an integrated circuit netlistRESHAPE INC·Filed 2001·Granted Apr 22, 2003·50 cites·18 claims
- 0789US4920477AVirtual address table look aside buffer miss recovery method and apparatusMULTIFLOW COMPUTER INC·Filed 1987·Granted Apr 24, 1990·120 cites·6 claims
- 0888US6574788B1Method and system for automatically generating low level program commands as dependency graphs from high level physical design stagesRESHAPE INC·Filed 2000·Granted Jun 3, 2003·72 cites·24 claims
- 0988US5057837AInstruction storage method with a compressed format using a mask wordDIGITAL EQUIPMENT CORP·Filed 1990·Granted Oct 15, 1991·139 cites·9 claims
- 1086US4747043AMultiprocessor cache coherence systemPRIME COMPUTER INC·Filed 1987·Granted May 24, 1988·90 cites·6 claims
- 1185US6564363B1Method and system for implementing a graphical user interface for defining and linking multiple attach points for multiple blocks of an integrated circuit netlistRESHAPE INC·Filed 2001·Granted May 13, 2003·35 cites·16 claims
- 1285US6564364B1Method and system for maintaining element abstracts of an integrated circuit netlist using a master library file and modifiable master library fileRESHAPE INC·Filed 2001·Granted May 13, 2003·36 cites·9 claims
- 1384US4587610AAddress translation systems for high speed computer memoriesPRIME COMPUTER INC·Filed 1984·Granted May 6, 1986·63 cites·17 claims
- 1483US7185305B1Creating a power distribution arrangement with tapered metal wires for a physical designMAGMA DESIGN AUTOMATION INC·Filed 2004·Granted Feb 27, 2007·22 cites·57 claims
- 1582US5604909AApparatus for processing instructions in a computing systemSILICON GRAPHICS COMPUTER SYST·Filed 1993·Granted Feb 18, 1997·79 cites·19 claims
- 1681US4561051AMemory access method and apparatus in multiple processor systemsPRIME COMPUTER INC·Filed 1984·Granted Dec 24, 1985·56 cites·12 claims
- 1780US8930594B1Integrated circuit with a pinmux crossbar and virtual pins for peripheral connectivityGOOGLE INC·Filed 2013·Granted Jan 6, 2015·5 cites·17 claims
- 1879US8130881B1MIMO with reduced compute complexityGOSSETT CARROLL PHILIP·Filed 2008·Granted Mar 6, 2012·7 cites·19 claims
- 1979US5510934AMemory system including local and global caches for storing floating point and integer dataSILICON GRAPHICS INC·Filed 1993·Granted Apr 23, 1996·87 cites·5 claims
- 2079US4750154AMemory alignment system and methodPRIME COMPUTER INC·Filed 1984·Granted Jun 7, 1988·58 cites·10 claims
- 2178US7114142B1Optimizing locations of pins for blocks in a hierarchical physical design by using physical design information of a prior hierarchical physical designMAGMA DESIGN AUTOMATION INC·Filed 2004·Granted Sep 26, 2006·15 cites·21 claims
- 2278US6865721B1Optimization of the top level in abutted-pin hierarchical physical designRESHAPE INC·Filed 2002·Granted Mar 8, 2005·18 cites·48 claims
- 2378US5954815AInvalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target addressSILICON GRAPHICS INC·Filed 1997·Granted Sep 21, 1999·65 cites·7 claims
- 2476US7155693B1Floorplanning a hierarchical physical design to improve placement and routingMAGMA DESIGN AUTOMATION INC·Filed 2004·Granted Dec 26, 2006·18 cites·12 claims
- 2574US6757874B1Facilitating verification in abutted-pin hierarchical physical designRESHAPE INC·Filed 2002·Granted Jun 29, 2004·13 cites·24 claims
- 2672US6247124B1Branch prediction entry with target line index calculated using relative position of second operation of two step branch operation in a line of instructionsMIPS TECH INC·Filed 1999·Granted Jun 12, 2001·47 cites·23 claims
- 2771US5537538ADebug mode for a superscalar RISC processorSILICON GRAPHICS INC·Filed 1993·Granted Jul 16, 1996·58 cites·4 claims
- 2866US6857116B1Optimization of abutted-pin hierarchical physical designRESHAPE INC·Filed 2000·Granted Feb 15, 2005·7 cites·52 claims
- 2965US5757658AProcedure and system for placement optimization of cells within circuit blocks by optimizing placement of input/output ports within an integrated circuit designSILICON GRAPHICS INC·Filed 1996·Granted May 26, 1998·56 cites·21 claims
- 3061US6854093B1Facilitating press operation in abutted-pin hierarchical physical designRESHAPE INC·Filed 2002·Granted Feb 8, 2005·5 cites·40 claims
- 3152US2024143885A1Multiply-Instantiated Block Modeling For Circuit Component Placement In Integrated CircuitGOOGLE LLC·Filed 2022·Application pending·0 cites
- 3250US2007136709A1Floorplanning A Hierarchical Physical Design To Improve Placement And RoutingMAGMA DESIGN AUTOMATION INC·Filed 2006·Application pending·0 cites
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