Inventor · disambiguated record
Fang Wen Tsai
Also filed as: TSAI FANG WEN
24 granted patents·2 pending applications·305 citations·filing 2003–2020
95Inventor score
Files withTAIWAN SEMICONDUCTOR MFG10TAIWAN SEMICONDUCTOR MFG CO LTD6CHANG HSIN2YU CHEN-HUA2CHAN BOR-WEN1
Top patents by PatentIndex Score
26 records- 0197US8900994B2Method for producing a protective structureYU CHEN-HUA·Filed 2011·Granted Dec 2, 2014·25 cites·20 claims
- 0297US8048810B2Method for metal gate N/P patterningTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Nov 1, 2011·137 cites·20 claims
- 0395US8928159B2Alignment marks in substrate having through-substrate via (TSV)CHANG HSIN·Filed 2010·Granted Jan 6, 2015·29 cites·20 claims
- 0491US7732344B1High selectivity etching process for metal gate N/P patterningTAIWAN SEMICONDUCTOR MFG·Filed 2009·Granted Jun 8, 2010·26 cites·20 claims
- 0589US8896136B2Alignment mark and method of formationTSAI CHEN-YU·Filed 2010·Granted Nov 25, 2014·10 cites·26 claims
- 0687US8922004B2Copper bump structures having sidewall protection layersLIN JING-CHENG·Filed 2010·Granted Dec 30, 2014·9 cites·20 claims
- 0784US9299676B2Through silicon via structureTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Mar 29, 2016·3 cites·20 claims
- 0884US8567837B2Reconfigurable guide pin design for centering wafers having different sizesCHANG HSIN·Filed 2010·Granted Oct 29, 2013·6 cites·13 claims
- 0983US8513107B2Replacement gate FinFET devices and methods for forming the sameCHAN BOR-WEN·Filed 2010·Granted Aug 20, 2013·8 cites·17 claims
- 1082US6953608B2Solution for FSG induced metal corrosion & metal peeling defects with extra bias liner and smooth RF bias ramp upTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Oct 11, 2005·31 cites·25 claims
- 1181US10692764B2Alignment marks in substrate having through-substrate via (TSV)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jun 23, 2020·2 cites·20 claims
- 1279US9478480B2Alignment mark and method of formationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Oct 25, 2016·3 cites·20 claims
- 1378US7626245B2Extreme low-k dielectric film scheme for advanced interconnectTAIWAN SEMICONDUCTOR MFG·Filed 2008·Granted Dec 1, 2009·7 cites·20 claims
- 1476US9093314B2Copper bump structures having sidewall protection layersTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jul 28, 2015·3 cites·20 claims
- 1570US10910267B2Alignment marks in substrate having through-substrate via (TSV)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Feb 2, 2021·0 cites·20 claims
- 1668US10163706B2Alignment marks in substrate having through-substrate via (TSV)TAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 25, 2018·1 cites·19 claims
- 1768USRE42514EExtreme low-K dielectric film scheme for advanced interconnectsTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Jul 5, 2011·2 cites·20 claims
- 1866US7465676B2Method for forming dielectric film to improve adhesion of low-k filmTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Dec 16, 2008·3 cites·23 claims
- 1958US9997497B2Through silicon via structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 12, 2018·0 cites·20 claims
- 2058US8952506B2Through silicon via structureTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Feb 10, 2015·0 cites·20 claims
- 2156US9633900B2Method for through silicon via structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Apr 25, 2017·0 cites·20 claims
- 2253US9099515B2Reconfigurable guide pin design for centering wafers having different sizesTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 4, 2015·0 cites·19 claims
- 2349US8980706B2Double treatment on hard mask for gate N/P patterningYEH MATT·Filed 2009·Granted Mar 17, 2015·0 cites·20 claims
- 2443US2008188074A1Peeling-free porous capping materialCHEN I-I·Filed 2007·Application pending·0 cites
- 2541US8691706B2Reducing substrate warpage in semiconductor processingYU CHEN-HUA·Filed 2012·Granted Apr 8, 2014·0 cites·16 claims
- 2634US2008116578A1Initiation layer for reducing stress transition due to curingWANG KUAN-CHEN·Filed 2006·Application pending·0 cites
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