Inventor · disambiguated record
Gilles S. C. Lamant
Also filed as: LAMANT GILLES · LAMANT GILLES S C
21 granted patents·1 pending application·271 citations·filing 2007–2019
95Inventor score
Top patents by PatentIndex Score
22 records- 0195US8516404B1Methods, systems, and articles of manufacture for implementing constraint checking windows for an electronic design for multiple-patterning lithography processesCAO MIN·Filed 2011·Granted Aug 20, 2013·15 cites·30 claims
- 0295US8046730B1Systems and methods of editing cells of an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Oct 25, 2011·60 cites·26 claims
- 0393US9684761B1Method for representing a photonic waveguide port and port specificationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jun 20, 2017·12 cites·19 claims
- 0491US9208277B1Automated adjustment of wire connections in computer-assisted design of circuitsLAMANT GILLES S C·Filed 2011·Granted Dec 8, 2015·20 cites·19 claims
- 0591US8726209B1Method and system for automatically establishing a component description format (CDF) debugging environmentLAMANT GILLES S C·Filed 2012·Granted May 13, 2014·23 cites·20 claims
- 0691US7949987B1Method and system for implementing abstract layout structures with parameterized cellsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted May 24, 2011·26 cites·20 claims
- 0789US7971175B2Method and system for implementing cached parameterized cellsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Jun 28, 2011·24 cites·32 claims
- 0887US9690893B1Methods and systems for customizable editing of completed chain of abutted instancesCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jun 27, 2017·8 cites·20 claims
- 0986US9053289B1Method and system for implementing an improved interface for designing electronic layoutsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 9, 2015·14 cites·30 claims
- 1086US7805698B1Methods and systems for physical hierarchy configuration engine and graphical editorCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Sep 28, 2010·26 cites·29 claims
- 1185US8364656B2Method and system for implementing multiuser cached parameterized cellsCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Jan 29, 2013·15 cites·25 claims
- 1275US10235490B1Methods and systems for centering of pins during instance abutmentCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 19, 2019·3 cites·20 claims
- 1373US8533650B2Annotation management for hierarchical designs of integrated circuitsARSINTESCU BOGDAN G·Filed 2009·Granted Sep 10, 2013·9 cites·21 claims
- 1468US10997349B1Incremental chaining in the presence of anchored figuresCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 4, 2021·1 cites·20 claims
- 1568US8694941B1System and method for abutment in the presence of dummy shapesBADEL OLIVIER·Filed 2012·Granted Apr 8, 2014·6 cites·18 claims
- 1667US9336123B1Method and system for automatically establishing a component description format (CDF) debugging environmentLAMANT GILLES S C·Filed 2014·Granted May 10, 2016·2 cites·9 claims
- 1766US7945890B2Registry for electronic design automation of integrated circuitsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted May 17, 2011·4 cites·21 claims
- 1863US7861205B2Spine selection mode for layout editingCADENCE DESIGN SYSTEMS INC·Filed 2008·Granted Dec 28, 2010·2 cites·20 claims
- 1955US9202000B1Implementing designs of guard ring and fill structures from simple unit cellsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 1, 2015·1 cites·19 claims
- 2052US8042088B2Method and system for implementing stacked viasCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Oct 18, 2011·0 cites·14 claims
- 2148US8402417B2Spine selection mode for layout editingLAMANT GILLES S C·Filed 2010·Granted Mar 19, 2013·0 cites·1 claims
- 2248US2012030644A1Method and system for implementing stacked viasLAMANT GILLES S C·Filed 2011·Application pending·0 cites
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