Inventor · disambiguated record
Daniel Pugh
Also filed as: PUGH DANIEL · PUGH DANIEL J
24 granted patents·1 pending application·234 citations·filing 2000–2024
96Inventor score
Top patents by PatentIndex Score
25 records- 0197US7372297B1Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resourcesTABULA INC·Filed 2005·Granted May 13, 2008·59 cites·21 claims
- 0296US10790830B1Fused memory and arithmetic circuitACHRONIX SEMICONDUCTOR CORP·Filed 2019·Granted Sep 29, 2020·19 cites·19 claims
- 0395US11650792B2Multiple mode arithmetic circuitACHRONIX SEMICONDUCTOR CORP·Filed 2022·Granted May 16, 2023·4 cites·20 claims
- 0494US12014150B2Multiple mode arithmetic circuitACHRONIX SEMICONDUCTOR CORP·Filed 2023·Granted Jun 18, 2024·2 cites·20 claims
- 0593US7971172B1IC that efficiently replicates a function to save logic and routing resourcesTABULA INC·Filed 2008·Granted Jun 28, 2011·22 cites·20 claims
- 0693US7587697B1System and method of mapping memory blocks in a configurable integrated circuitTABULA INC·Filed 2006·Granted Sep 8, 2009·33 cites·10 claims
- 0792US11288220B2Cascade communications between FPGA tilesACHRONIX SEMICONDUCTOR CORP·Filed 2019·Granted Mar 29, 2022·7 cites·20 claims
- 0890US11256476B2Multiple mode arithmetic circuitACHRONIX SEMICONDUCTOR CORP·Filed 2019·Granted Feb 22, 2022·5 cites·20 claims
- 0987US12034446B2Fused memory and arithmetic circuitACHRONIX SEMICONDUCTOR CORP·Filed 2020·Granted Jul 9, 2024·2 cites·20 claims
- 1086US11734216B2Cascade communications between FPGA tilesACHRONIX SEMICONDUCTOR CORP·Filed 2022·Granted Aug 22, 2023·1 cites·20 claims
- 1182US12468506B2Multiple mode arithmetic circuitACHRONIX SEMICONDUCTOR CORP·Filed 2024·Granted Nov 11, 2025·0 cites·18 claims
- 1281US7930666B1System and method of providing a memory hierarchyTABULA INC·Filed 2006·Granted Apr 19, 2011·11 cites·18 claims
- 1379US8463836B1Performing mathematical and logical operations in multiple sub-cyclesPUGH DANIEL J·Filed 2005·Granted Jun 11, 2013·13 cites·30 claims
- 1477US12141088B2Cascade communications between FPGA tilesACHRONIX SEMICONDUCTOR CORP·Filed 2023·Granted Nov 12, 2024·0 cites·20 claims
- 1577US7818361B1Method and apparatus for performing two's complement multiplicationTABULA INC·Filed 2005·Granted Oct 19, 2010·8 cites·14 claims
- 1673US7765249B1Use of hybrid interconnect/logic circuits for multiplicationTABULA INC·Filed 2005·Granted Jul 27, 2010·6 cites·21 claims
- 1771US6834291B1Gold code generator designINTEL CORP·Filed 2000·Granted Dec 21, 2004·15 cites·26 claims
- 1870US8434045B1System and method of providing a memory hierarchySCHMIT HERMAN·Filed 2011·Granted Apr 30, 2013·2 cites·9 claims
- 1969US6801052B2Field programmable gate array core cell with efficient logic packingLEOPARD LOGIC INC·Filed 2002·Granted Oct 5, 2004·14 cites·14 claims
- 2068US10656915B2Efficient FPGA multipliersACHRONIX SEMICONDUCTOR CORP·Filed 2018·Granted May 19, 2020·1 cites·20 claims
- 2162US10963221B2Efficient FPGA multipliersACHRONIX SEMICONDUCTOR CORP·Filed 2020·Granted Mar 30, 2021·0 cites·20 claims
- 2254US7009421B2Field programmable gate array core cell with efficient logic packingAGATE LOGIC INC·Filed 2004·Granted Mar 7, 2006·4 cites·13 claims
- 2354US2025265015A1Fpga memory with auto address modeACHRONIX SEMICONDUCTOR CORP·Filed 2024·Application pending·0 cites
- 2452US7080107B2Gold code generator designINTEL CORP·Filed 2004·Granted Jul 18, 2006·2 cites·13 claims
- 2548US6904105B1Method and implemention of a traceback-free parallel viterbi decoderINTEL CORP·Filed 2000·Granted Jun 7, 2005·4 cites·19 claims
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