Inventor · disambiguated record
Kiyohito Mukai
Also filed as: MUKAI KIYOHITO
11 granted patents·7 pending applications·167 citations·filing 1999–2009
91Inventor score
Top patents by PatentIndex Score
18 records- 0189US7174527B2Layout verification method and method for designing semiconductor integrated circuit device using the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2005·Granted Feb 6, 2007·18 cites·17 claims
- 0284US6576147B2Method of layout compactionMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2002·Granted Jun 10, 2003·22 cites·7 claims
- 0382US8024689B2Semiconductor integrated circuit apparatus with low wiring resistancePANASONIC CORP·Filed 2007·Granted Sep 20, 2011·12 cites·17 claims
- 0480US7062732B2Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device for generating pattern used for semiconductor deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Jun 13, 2006·30 cites·21 claims
- 0576US7171645B2Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device and device of generating pattern used for semiconductor deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Jan 30, 2007·22 cites·18 claims
- 0675US6303251B1Mask pattern correction process, photomask and semiconductor integrated circuit deviceMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1999·Granted Oct 16, 2001·37 cites·12 claims
- 0771US6473882B2Method of layout compactionMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2001·Granted Oct 29, 2002·10 cites·7 claims
- 0863US7269807B2Area ratio/occupancy ratio verification method and pattern generation methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2004·Granted Sep 11, 2007·10 cites·13 claims
- 0950US2007136702A1Semiconductor device layout inspection methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2007·Application pending·0 cites
- 1046US7707523B2Method of fabricating a semiconductor device and a method of generating a mask patternPANASONIC CORP·Filed 2006·Granted Apr 27, 2010·0 cites·3 claims
- 1146US2004139407A1Semiconductor device layout inspection methodMUKAI KIYOHITO·Filed 2003·Application pending·0 cites
- 1245US7115478B2Method of fabricating a semiconductor device and a method of generating a mask patternMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2003·Granted Oct 3, 2006·2 cites·6 claims
- 1345US2008209367A1Reliability design methodMUKAI KIYOHITO·Filed 2008·Application pending·0 cites
- 1444US2010242011A1Method for verification of mask layout of semiconductor integrated circuitMUKAI KIYOHITO·Filed 2009·Application pending·0 cites
- 1540US2005224914A1Semiconductor integrated circuit device, method of enerating pattern thereof, method of manufacturing the same, and pattern generating apparatus for the sameMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2005·Application pending·0 cites
- 1636US6183920B1Semiconductor device geometrical pattern correction process and geometrical pattern extraction processMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 1999·Granted Feb 6, 2001·4 cites·21 claims
- 1736US2005204327A1Layout data verification method, mask pattern verification method and circuit operation verification methodMATSUSHITA ELECTRIC INDUSTRIAL CO LTD·Filed 2005·Application pending·0 cites
- 1831US2006197573A1Semiconductor integrated circuit and method for manufacturing semiconductor integrated circuitMATSUMURA YOICHI·Filed 2006·Application pending·0 cites
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