Inventor · disambiguated record
Colyn S. Case
Also filed as: CASE COLYN · CASE COLYN S · CASE COLYN SCOTT
27 granted patents·1 pending application·1,512 citations·filing 1991–2015
98Inventor score
Top patents by PatentIndex Score
28 records- 0197US7469311B1Asymmetrical busNVIDIA CORP·Filed 2006·Granted Dec 23, 2008·76 cites·17 claims
- 0295US7624221B1Control device for data stream optimizations in a link interfaceNVIDIA CORP·Filed 2006·Granted Nov 24, 2009·51 cites·22 claims
- 0395US7278008B1Virtual address translation system with caching of variable-range translation clustersNVIDIA CORP·Filed 2004·Granted Oct 2, 2007·114 cites·33 claims
- 0494US7562205B1Virtual address translation system with caching of variable-range translation clustersNVIDIA CORP·Filed 2007·Granted Jul 14, 2009·34 cites·15 claims
- 0594US7415575B1Shared cache with client-specific replacement policyNVIDIA CORP·Filed 2005·Granted Aug 19, 2008·61 cites·17 claims
- 0694US7334108B1Multi-client virtual address translation system with translation units of variable-range sizeNVIDIA CORP·Filed 2004·Granted Feb 19, 2008·108 cites·26 claims
- 0793US7526593B2Packet combiner for a packetized bus with dynamic holdoff timeNVIDIA CORP·Filed 2006·Granted Apr 28, 2009·46 cites·20 claims
- 0893US7386697B1Memory management for virtual address space with translation units of variable range sizeNVIDIA CORP·Filed 2005·Granted Jun 10, 2008·80 cites·21 claims
- 0993US7296139B1In-memory table structure for virtual address translation system with translation units of variable range sizeNVIDIA CORP·Filed 2004·Granted Nov 13, 2007·70 cites·25 claims
- 1090US5321810AAddress method for computer graphics systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jun 14, 1994·93 cites·11 claims
- 1190US5315698AMethod and apparatus for varying command length in a computer graphics systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted May 24, 1994·93 cites·8 claims
- 1289US8341380B2Efficient memory translator with variable size cache line coverageDEMING JAMES LEROY·Filed 2010·Granted Dec 25, 2012·22 cites·20 claims
- 1389US5321806AMethod and apparatus for transmitting graphics command in a computer graphics systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jun 14, 1994·129 cites·10 claims
- 1488US7788439B1Asymmetrical bus for bus link width optimization of a graphics systemNVIDIA CORP·Filed 2008·Granted Aug 31, 2010·16 cites·18 claims
- 1588US6820173B1Data prefetcher with predictor capabilitiesNVIDIA CORP·Filed 2001·Granted Nov 16, 2004·59 cites·33 claims
- 1686US5911051AHigh-throughput interconnect allowing bus transactions based on partial access requestsINTEL CORP·Filed 1996·Granted Jun 8, 1999·124 cites·34 claims
- 1784US7797510B1Memory management for virtual address space with translation units of variable range sizeNVIDIA CORP·Filed 2008·Granted Sep 14, 2010·14 cites·16 claims
- 1881US5315696AGraphics command processing method in a computer graphics systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted May 24, 1994·58 cites·3 claims
- 1981US5313577ATranslation of virtual addresses in a computer graphics systemDIGITAL EQUIPMENT CORP·Filed 1991·Granted May 17, 1994·61 cites·6 claims
- 2080US8161252B1Memory interface with dynamic selection among mirrored storage locationsCASE COLYN S·Filed 2005·Granted Apr 17, 2012·15 cites·14 claims
- 2179US7664905B2Page stream sorter for poor locality access patternsNVIDIA CORP·Filed 2006·Granted Feb 16, 2010·11 cites·22 claims
- 2272US6044419AMemory handling system that backfills dual-port buffer from overflow buffer when dual-port buffer is no longer fullINTEL CORP·Filed 1997·Granted Mar 28, 2000·61 cites·18 claims
- 2370US6317803B1High-throughput interconnect having pipelined and non-pipelined bus transaction modesINTEL CORP·Filed 1996·Granted Nov 13, 2001·57 cites·35 claims
- 2470US6097402ASystem and method for placement of operands in system memoryINTEL CORP·Filed 1998·Granted Aug 1, 2000·54 cites·21 claims
- 2566US8035647B1Raster operations unit with interleaving of read and write requests using PCI expressNVIDIA CORP·Filed 2006·Granted Oct 11, 2011·5 cites·20 claims
- 2642US2008028181A1Dedicated mechanism for page mapping in a gpuNVIDIA CORP·Filed 2007·Application pending·0 cites
- 2738US9262837B2PCIE clock rate stepping for graphics and platform processorsNVIDIA CORP·Filed 2015·Granted Feb 16, 2016·0 cites·21 claims
- 2835US9098383B1Consolidated crossbar that supports a multitude of traffic typesTREICHLER SEAN J·Filed 2010·Granted Aug 4, 2015·0 cites·18 claims
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