Inventor
ROTONDARO ANTONIO LUIS PACHECO
US24 patents
⚠️ This page may combine multiple inventors who share the name “ROTONDARO ANTONIO LUIS PACHECO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TEXAS INSTRUMENTS INC
17 patentsUS6696332B2Feb 24, 2004
Bilayer deposition to avoid unwanted interfacial reactions during high K gate dielectric processing
TEXAS INSTRUMENTS INC145 citations99
US6750126B1Jun 15, 2004
Methods for sputter deposition of high-k dielectric films
TEXAS INSTRUMENTS INC83 citations98
US6656852B2Dec 2, 2003
Method for the selective removal of high-k dielectrics
TEXAS INSTRUMENTS INC62 citations96
US6787425B1Sep 7, 2004
Methods for fabricating transistor gate structures
TEXAS INSTRUMENTS INC27 citations89
US7226826B2Jun 5, 2007
Semiconductor device having multiple work functions and method of manufacture therefor
TEXAS INSTRUMENTS INC14 citations84
US7528072B2May 5, 2009
Crystallographic preferential etch to define a recessed-region for epitaxial growth
TEXAS INSTRUMENTS INC9 citations82
US7514309B2Apr 7, 2009
Methods to selectively protect NMOS regions, PMOS regions, and gate layers during EPI process
TEXAS INSTRUMENTS INC9 citations82
US7601577B2Oct 13, 2009
Work function control of metals
TEXAS INSTRUMENTS INC7 citations74
US7026218B2Apr 11, 2006
Use of indium to define work function of p-type doped polysilicon
TEXAS INSTRUMENTS INC9 citations74
US7088123B1Aug 8, 2006
System and method for extraction of C-V characteristics of ultra-thin oxides
TEXAS INSTRUMENTS INC10 citations70
US7172936B2Feb 6, 2007
Method to selectively strain NMOS devices using a cap poly layer
TEXAS INSTRUMENTS INC6 citations63
US8384138B2Feb 26, 2013
Defect prevention on SRAM cells that incorporate selective epitaxial regions
TEXAS INSTRUMENTS INC2 citations62
US7691714B2Apr 6, 2010
Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor
TEXAS INSTRUMENTS INC6 citations62
US7601578B2Oct 13, 2009
Defect control in gate dielectrics
TEXAS INSTRUMENTS INC1 citations52
US7071519B2Jul 4, 2006
Control of high-k gate dielectric film composition profile for property optimization
TEXAS INSTRUMENTS INC0 citations52
US6803611B2Oct 12, 2004
Use of indium to define work function of p-type doped polysilicon
TEXAS INSTRUMENTS INC1 citations52
US7199011B2Apr 3, 2007
Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
TEXAS INSTRUMENTS INC1 citations45
TOKYO ELECTRON LTD
7 patentsUS12226796B2Feb 18, 2025
Bath systems and methods thereof
TOKYO ELECTRON LTD0 citations60
US11738363B2Aug 29, 2023
Bath systems and methods thereof
TOKYO ELECTRON LTD1 citations60
US12002687B2Jun 4, 2024
System and methods for wafer drying
TOKYO ELECTRON LTD0 citations56
US11515178B2Nov 29, 2022
System and methods for wafer drying
TOKYO ELECTRON LTD0 citations56
US10096480B2Oct 9, 2018
Method and apparatus for dynamic control of the temperature of a wet etch process
TOKYO ELECTRON LTD0 citations51
US10256163B2Apr 9, 2019
Method of treating a microelectronic substrate using dilute TMAH
TOKYO ELECTRON LTD0 citations50
US11376640B2Jul 5, 2022
Apparatus and method to electrostatically remove foreign matter from substrate surfaces
TOKYO ELECTRON LTD0 citations47