Inventor · disambiguated record
Chung-Min Fu
Also filed as: FU CHUNG-MIN
28 granted patents·1 pending application·344 citations·filing 2004–2015
96Inventor score
Files withTAIWAN SEMICONDUCTOR MFG11TAIWAN SEMICONDUCTOR MFG CO LTD7FU CHUNG-MIN6CHEN HUANG-YU1CHEN WEN-HAO1
Top patents by PatentIndex Score
29 records- 0197US8701073B1System and method for across-chip thermal and power management in stacked IC designsTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Apr 15, 2014·72 cites·17 claims
- 0296US7378720B2Integrated stress relief pattern and registration structureTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted May 27, 2008·54 cites·11 claims
- 0393US8631372B2System and method of electromigration mitigation in stacked IC designsYU CHI-YEH·Filed 2012·Granted Jan 14, 2014·45 cites·17 claims
- 0492US9367655B2Topography-aware lithography pattern checkSHIH I-CHANG·Filed 2012·Granted Jun 14, 2016·69 cites·20 claims
- 0589US8978003B1Method of making semiconductor device and a control system for performing the sameTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Mar 10, 2015·10 cites·20 claims
- 0686US9223919B2System and method of electromigration mitigation in stacked IC designsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Dec 29, 2015·9 cites·18 claims
- 0784US9318504B2Density gradient cell arrayTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Apr 19, 2016·4 cites·20 claims
- 0884US8977991B2Method and system for replacing a pattern in a layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Mar 10, 2015·6 cites·20 claims
- 0983US8601408B2Method and system for replacing a pattern in a layoutCHEN HUANG-YU·Filed 2011·Granted Dec 3, 2013·6 cites·19 claims
- 1081US9768119B2Apparatus and method for mitigating dynamic IR voltage drop and electromigration affectsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Sep 19, 2017·6 cites·17 claims
- 1180US8901492B1Three-dimensional semiconductor image reconstruction apparatus and methodTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 2, 2014·4 cites·20 claims
- 1278US9324178B2Three-dimensional semiconductor image reconstruction apparatus and methodTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 26, 2016·3 cites·20 claims
- 1378US8677292B2Cell-context aware integrated circuit designFU CHUNG-MIN·Filed 2010·Granted Mar 18, 2014·6 cites·26 claims
- 1476US9245073B2Pattern density-dependent mismatch modeling flowTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jan 26, 2016·4 cites·15 claims
- 1576US8726200B2Recognition of template patterns with mask informationFU CHUNG-MIN·Filed 2011·Granted May 13, 2014·4 cites·20 claims
- 1675US7202550B2Integrated stress relief pattern and registration structureTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Apr 10, 2007·20 cites·31 claims
- 1774US9311440B2System and method of electromigration avoidance for automatic place-and-routeKAO JERRY·Filed 2012·Granted Apr 12, 2016·5 cites·20 claims
- 1871US8577717B2Method and system for predicting shrinkable yield for business assessment of integrated circuit design shrinkFU CHUNG-MIN·Filed 2006·Granted Nov 5, 2013·3 cites·11 claims
- 1970US9262568B2Dummy pattern performance aware analysis and implementationFU CHUNG-MIN·Filed 2010·Granted Feb 16, 2016·3 cites·19 claims
- 2069US9147694B2Density gradient cell arrayTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Sep 29, 2015·2 cites·20 claims
- 2167US9141745B2Method and system for designing Fin-FET semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Sep 22, 2015·2 cites·17 claims
- 2266US8726208B2DFM improvement utility with unified interfaceCHEN WEN-HAO·Filed 2011·Granted May 13, 2014·2 cites·16 claims
- 2361US7356787B2Alternative methodology for defect simulation and systemTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Apr 8, 2008·5 cites·15 claims
- 2458US9122836B2Recognition of template patterns with mask informationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Sep 1, 2015·0 cites·20 claims
- 2552US9639647B2Method of making semiconductor device and system for performing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 2, 2017·0 cites·20 claims
- 2650US9582633B23D device modeling for FinFET devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Feb 28, 2017·0 cites·20 claims
- 2749US8782593B2Thermal analysis of integrated circuit packagesTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Jul 15, 2014·0 cites·19 claims
- 2845US2009055782A1Secure Yield-aware Design Flow with Annotated Design LibrariesFU CHUNG-MIN·Filed 2007·Application pending·0 cites
- 2944US8786094B2Semiconductor devices and methods of manufacture thereofFU CHUNG-MIN·Filed 2012·Granted Jul 22, 2014·0 cites·20 claims
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