Inventor · disambiguated record
Philip G. Shephard, Iii
Also filed as: SHEPHARD III PHILIP G · SHEPHARD III PHILIP GEORGE · SHEPHARD PHILIP G III
14 granted patents·1 pending application·277 citations·filing 1993–2008
93Inventor score
Files withIBM15
Top patents by PatentIndex Score
15 records- 0183US6662133B2JTAG-based software to perform cumulative array repairIBM·Filed 2001·Granted Dec 9, 2003·43 cites·25 claims
- 0283US6553527B1Programmable array built-in self test method and controller with programmable expect generatorIBM·Filed 1999·Granted Apr 22, 2003·54 cites·19 claims
- 0371US6553525B1Method and apparatus for selectively enabling and disabling functions on a per array basisIBM·Filed 1999·Granted Apr 22, 2003·31 cites·21 claims
- 0470US7073106B2Test method for guaranteeing full stuck-at-fault coverage of a memory arrayIBM·Filed 2003·Granted Jul 4, 2006·18 cites·36 claims
- 0567US7552413B2System and computer program for verifying performance of an array by simulating operation of edge cells in a full array modelIBM·Filed 2008·Granted Jun 23, 2009·3 cites·13 claims
- 0665US5633877AProgrammable built-in self test method and controller for arraysIBM·Filed 1995·Granted May 27, 1997·52 cites·18 claims
- 0764US7474574B1Shift register latch with embedded dynamic random access memory scan only cellIBM·Filed 2007·Granted Jan 6, 2009·5 cites·7 claims
- 0863US5375091AMethod and apparatus for memory dynamic burn-in and testIBM·Filed 1993·Granted Dec 20, 1994·23 cites·22 claims
- 0959US7424691B2Method for verifying performance of an array by simulating operation of edge cells in a full array modelIBM·Filed 2006·Granted Sep 9, 2008·1 cites·7 claims
- 1058US7870515B2System and method for improved hierarchical analysis of electronic circuitsIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 1155US6553526B1Programmable array built-in self test method and system for arrays with imbedded logicIBM·Filed 1999·Granted Apr 22, 2003·18 cites·32 claims
- 1251US6564344B1System and method of generating dynamic word line from the content addressable memory (CAM) “hit/miss” signal which is scannable for testabilityIBM·Filed 1999·Granted May 13, 2003·15 cites·31 claims
- 1347US6523145B1Method and apparatus for testing a contents-addressable-memory-type structure using a simultaneous write-thru modeIBM·Filed 1999·Granted Feb 18, 2003·12 cites·9 claims
- 1444US7099201B1Multifunctional latch circuit for use with both SRAM array and self test deviceIBM·Filed 2005·Granted Aug 29, 2006·1 cites·20 claims
- 1542US2007234253A1Multiple mode approach to building static timing models for digital transistor circuitsIBM·Filed 2006·Application pending·0 cites
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