Inventor · disambiguated record
Jose Angel Paredes
Also filed as: PAREDES JOSE A · PAREDES JOSE A BAIOCCHI · PAREDES JOSE ANGEL
35 granted patents·3 pending applications·267 citations·filing 1999–2016
97Inventor score
Top patents by PatentIndex Score
38 records- 0192US7467325B2Processor instruction retry recoveryIBM·Filed 2005·Granted Dec 16, 2008·26 cites·12 claims
- 0291US9934033B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 3, 2018·8 cites·11 claims
- 0389US9940133B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 10, 2018·6 cites·6 claims
- 0488US9985656B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·7 cites·6 claims
- 0584US9985655B2Generating ECC values for byte-write capable registersIBM·Filed 2015·Granted May 29, 2018·6 cites·11 claims
- 0684US7827443B2Processor instruction retry recoveryIBM·Filed 2008·Granted Nov 2, 2010·12 cites·19 claims
- 0778US9229524B2Performing local power gating in a processorBONEN NADAV·Filed 2012·Granted Jan 5, 2016·3 cites·17 claims
- 0876US10176038B2Partial ECC mechanism for a byte-write capable registerIBM·Filed 2015·Granted Jan 8, 2019·2 cites·20 claims
- 0975US6640293B1Apparatus and method of utilizing Alias Hit signals to detect errors within the real address tag arraysIBM·Filed 2000·Granted Oct 28, 2003·21 cites·15 claims
- 1074US6826090B1Apparatus and method for a radiation resistant latchIBM·Filed 2003·Granted Nov 30, 2004·21 cites·20 claims
- 1173US7506230B2Transient noise detection scheme and apparatusIBM·Filed 2005·Granted Mar 17, 2009·6 cites·10 claims
- 1272US7679973B2Register fileIBM·Filed 2008·Granted Mar 16, 2010·5 cites·12 claims
- 1372US7202704B2Leakage sensing and keeper circuit for proper operation of a dynamic circuitIBM·Filed 2004·Granted Apr 10, 2007·14 cites·20 claims
- 1472US6825691B1Apparatus and method for a radiation resistant latch with integrated scanIBM·Filed 2003·Granted Nov 30, 2004·19 cites·20 claims
- 1570US7073106B2Test method for guaranteeing full stuck-at-fault coverage of a memory arrayIBM·Filed 2003·Granted Jul 4, 2006·18 cites·36 claims
- 1668US7116569B2Method and apparatus for selecting operating characteristics of a content addressable memory by using a compare maskIBM·Filed 2005·Granted Oct 3, 2006·7 cites·20 claims
- 1767US7478276B2Method for checkpointing instruction groups with out-of-order floating point instructions in a multi-threaded processorIBM·Filed 2005·Granted Jan 13, 2009·4 cites·9 claims
- 1858US6934181B2Reducing sub-threshold leakage in a memory arrayIBM·Filed 2003·Granted Aug 23, 2005·9 cites·16 claims
- 1956US7443737B2Register fileIBM·Filed 2004·Granted Oct 28, 2008·5 cites·6 claims
- 2055US6914450B2Register-file bit-read method and apparatusIBM·Filed 2003·Granted Jul 5, 2005·8 cites·20 claims
- 2152US6477635B1Data processing system including load/store unit having a real address tag array and method for correcting effective address aliasingIBM·Filed 1999·Granted Nov 5, 2002·25 cites·14 claims
- 2250US7085896B2Method and apparatus which implements a multi-ported LRU in a multiple-clock systemIBM·Filed 2003·Granted Aug 1, 2006·3 cites·14 claims
- 2350US6353558B1Method and apparatus for writing to memory cellsIBM·Filed 2000·Granted Mar 5, 2002·6 cites·19 claims
- 2449US6341095B1Apparatus for increasing pulldown rate of a bitline in a memory device during a read operationIBM·Filed 2001·Granted Jan 22, 2002·6 cites·20 claims
- 2548US7012839B1Register file apparatus and method incorporating read-after-write blocking using detection cellsIBM·Filed 2004·Granted Mar 14, 2006·4 cites·15 claims
- 2646US9766975B2Partial ECC handling for a byte-write capable registerIBM·Filed 2015·Granted Sep 19, 2017·0 cites·20 claims
- 2745US7683662B2Method and apparatus for implementing complex logic within a memory arrayIBM·Filed 2008·Granted Mar 23, 2010·1 cites·8 claims
- 2845US7471103B2Method for implementing complex logic within a memory arrayIBM·Filed 2006·Granted Dec 30, 2008·1 cites·8 claims
- 2944US7002860B2Multilevel register-file bit-read method and apparatusIBM·Filed 2003·Granted Feb 21, 2006·4 cites·9 claims
- 3042US7561489B2System and method of selective row energization based on write dataIBM·Filed 2008·Granted Jul 14, 2009·0 cites·15 claims
- 3140US7379348B2System and method of selective row energization based on write dataIBM·Filed 2006·Granted May 27, 2008·0 cites·2 claims
- 3240US7142463B2Register file method incorporating read-after-write blocking using detection cellsIBM·Filed 2005·Granted Nov 28, 2006·0 cites·7 claims
- 3340US6737888B1Method for skipping a latch in timing-sensitive dynamic circuits of a multi-clocked system with unspecific underlap requirementIBM·Filed 1999·Granted May 18, 2004·5 cites·8 claims
- 3439US6236253B1Apparatus and method for controlling a reset in a self-timed circuit of a multiple-clock systemIBM·Filed 1999·Granted May 22, 2001·5 cites·20 claims
- 3538US2017109093A1Method and apparatus for writing a portion of a register in a microprocessorIBM·Filed 2015·Application pending·0 cites
- 3637US2007229132A1Scannable domino latch redundancy for soft error rate protection with collision avoidanceCHU SAM G·Filed 2006·Application pending·0 cites
- 3735US7015723B2Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluationIBM·Filed 2004·Granted Mar 21, 2006·0 cites·20 claims
- 3835US2008123437A1Apparatus for Floating Bitlines in Static Random Access Memory ArraysAGARWAL VIKAS·Filed 2006·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →