Inventor · disambiguated record
Sreedhar Ravipalli
Also filed as: RAVIPALLI SREEDHAR
7 granted patents·6 pending applications·15 citations·filing 2013–2024
75Inventor score
Top patents by PatentIndex Score
13 records- 0191US10397115B1Longest prefix matching providing packet processing and/or memory efficiencies in processing of packetsCISCO TECH INC·Filed 2018·Granted Aug 27, 2019·13 cites·20 claims
- 0276US11593273B2Management of cache use requests sent to remote cache devicesINTEL CORP·Filed 2019·Granted Feb 28, 2023·2 cites·20 claims
- 0368US2024347514A1Stacked die network interface controller circuitryINTEL CORP·Filed 2024·Application pending·0 cites
- 0461US12481345B2Techniques for power management in compute circuitsINTEL CORP·Filed 2022·Granted Nov 25, 2025·0 cites·20 claims
- 0560US12046578B2Stacked die network interface controller circuitryINTEL CORP·Filed 2020·Granted Jul 23, 2024·0 cites·31 claims
- 0655US10715439B2Longest prefix matching providing packet processing and/or memory efficiencies in processing of packetsCISCO TECH INC·Filed 2019·Granted Jul 14, 2020·0 cites·16 claims
- 0752US2022334983A1Techniques For Sharing Memory Interface Circuits Between Integrated Circuit DiesINTEL CORP·Filed 2022·Application pending·0 cites
- 0851US12476639B2Chained command architecture for packet processingINTEL CORP·Filed 2022·Granted Nov 18, 2025·0 cites·20 claims
- 0949US2023018793A1Programmable Input And Output Interfaces In Processing Integrated Circuits For Servers And Other DevicesINTEL CORP·Filed 2022·Application pending·0 cites
- 1049US2023035058A1Techniques For Booting A Compute Integrated Circuit Using A Boot Management Controller In A Processing Integrated CircuitINTEL CORP·Filed 2022·Application pending·0 cites
- 1148US2022334979A1Crossbar Circuits And Methods For External Communication With Logic In Integrated CircuitsINTEL CORP·Filed 2022·Application pending·0 cites
- 1244US2023027807A1Method and Apparatus to Enable CPU Host-Unaware Dynamic FPGA ReconfigurationPAL RAHUL·Filed 2022·Application pending·0 cites
- 1329US9276867B2Hierarchical scheduling system with layer bypass including updating scheduling information of a scheduling layer for each item whether or not it bypasses the scheduling layerRAMCHANDANI RATAN·Filed 2013·Granted Mar 1, 2016·0 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →