Inventor · disambiguated record
Deanna Postles Dunn Berger
Also filed as: DUNN BERGER DEANNA POSTLES
11 granted patents·22 citations·filing 2010–2019
85Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0179US8996819B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2012·Granted Mar 31, 2015·4 cites·7 claims
- 0279US8447905B2Dynamic multi-level cache including resource access fairness schemeAMBROLADZE EKATERINA M·Filed 2010·Granted May 21, 2013·6 cites·15 claims
- 0378US8352687B2Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchyIBM·Filed 2010·Granted Jan 8, 2013·4 cites·7 claims
- 0477US10540251B2Accuracy sensitive performance countersIBM·Filed 2017·Granted Jan 21, 2020·2 cites·20 claims
- 0574US8566532B2Management of multipurpose command queues in a multilevel cache hierarchyDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Oct 22, 2013·4 cites·18 claims
- 0666US8407420B2System, apparatus and method utilizing early access to shared cache pipeline for latency reductionDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Mar 26, 2013·2 cites·19 claims
- 0760US10884890B2Accuracy sensitive performance countersIBM·Filed 2019·Granted Jan 5, 2021·0 cites·20 claims
- 0853US8706972B2Dynamic mode transitions for cache instructionsIBM·Filed 2012·Granted Apr 22, 2014·0 cites·7 claims
- 0951US8539190B2Preemptive in-pipeline store compare resolutionDUNN BERGER DEANNA POSTLES·Filed 2012·Granted Sep 17, 2013·0 cites·19 claims
- 1046US8635409B2Dynamic mode transitions for cache instructionsDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Jan 21, 2014·0 cites·15 claims
- 1146US8407442B2Preemptive in-pipeline store compare resolutionDUNN BERGER DEANNA POSTLES·Filed 2010·Granted Mar 26, 2013·0 cites·19 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →