Inventor · disambiguated record
Michael L. Ziegler
Also filed as: ZIEGLER II MICHAEL L · ZIEGLER MICHAEL · ZIEGLER MICHAEL L
45 granted patents·6 pending applications·1,614 citations·filing 1980–2022
98Inventor score
Files withHEWLETT PACKARD CO12ZIEGLER MICHAEL L12HEWLETT PACKARD DEVELOPMENT CO9DATA GENERAL CORP6ALLIANT COMPUTER SYSTEMS3
Top patents by PatentIndex Score
51 records- 0191US7771659B2Arrangement and method for the analysis of body fluidsPVT PROBENVERTEILTECHNIK GMBH·Filed 2003·Granted Aug 10, 2010·65 cites·14 claims
- 0291US6708288B1Compiler-based checkpointing for support of error recoveryHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 16, 2004·74 cites·13 claims
- 0389US8940252B2Rack apparatus for a sample distribution systemZIEGLER MICHAEL·Filed 2009·Granted Jan 27, 2015·17 cites·13 claims
- 0489US4794521ADigital computer with cache capable of concurrently handling multiple accesses from parallel processorsALLIANT COMPUTER SYSTEMS·Filed 1985·Granted Dec 27, 1988·142 cites·11 claims
- 0588US9237082B2Packet descriptor trace indicatorsZIEGLER MICHAEL L·Filed 2012·Granted Jan 12, 2016·12 cites·15 claims
- 0688US6874138B1Method and apparatus for resuming execution of a failed computer programHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 29, 2005·56 cites·22 claims
- 0788US5586297APartial cache line write transactions in a computing system with a write back cacheHEWLETT PACKARD CO·Filed 1994·Granted Dec 17, 1996·139 cites·12 claims
- 0888US5530933AMultiprocessor system for maintaining cache coherency by checking the coherency in the order of the transactions being issued on the busHEWLETT PACKARD CO·Filed 1994·Granted Jun 25, 1996·139 cites·4 claims
- 0985US8689049B2Corrective actions based on probabilitiesZIEGLER MICHAEL L·Filed 2011·Granted Apr 1, 2014·13 cites·15 claims
- 1085US4513372AUniversal memoryDATA GENERAL CORP·Filed 1982·Granted Apr 23, 1985·45 cites·10 claims
- 1181US6473845B1System and method for dynamically updating memory address mappingsHEWLETT PACKARD CO·Filed 2000·Granted Oct 29, 2002·36 cites·15 claims
- 1281US4783736ADigital computer with multisection cacheALLIANT COMPUTER SYSTEMS·Filed 1985·Granted Nov 8, 1988·74 cites·24 claims
- 1380US4386399AData processing systemDATA GENERAL CORP·Filed 1980·Granted May 31, 1983·61 cites·6 claims
- 1480US4380812ARefresh and error detection and correction technique for a data processing systemDATA GENERAL CORP·Filed 1980·Granted Apr 19, 1983·62 cites·6 claims
- 1579US9112820B2Delay queues based on delay remainingZIEGLER MICHAEL L·Filed 2012·Granted Aug 18, 2015·5 cites·10 claims
- 1678US9426083B2Consistency checking for credit-based control of data communicationsZIEGLER MICHAEL L·Filed 2009·Granted Aug 23, 2016·7 cites·20 claims
- 1777US6199144B1Method and apparatus for transferring data in a computer systemINTEL CORP·Filed 1997·Granted Mar 6, 2001·77 cites·20 claims
- 1877US5535352AAccess hints for input/output address translation mechanismsHEWLETT PACKARD CO·Filed 1994·Granted Jul 9, 1996·79 cites·9 claims
- 1975US8209236B2Merchandise tracking and ordering systemSTONE REBECCA LYNN·Filed 2007·Granted Jun 26, 2012·19 cites·49 claims
- 2075US6304932B1Queue-based predictive flow control mechanism with indirect determination of queue fullnessHEWLETT PACKARD CO·Filed 2000·Granted Oct 16, 2001·19 cites·3 claims
- 2174US6128706AApparatus and method for a load bias--load with intent to semaphoreINST THE DEV OF EMERGING ARCHI·Filed 1998·Granted Oct 3, 2000·68 cites·15 claims
- 2273US5133059AComputer with multiple processors having varying priorities for access to a multi-element memoryALLIANT COMPUTER SYSTEMS·Filed 1991·Granted Jul 21, 1992·65 cites·14 claims
- 2371US7191319B1System and method for preloading cache memory in response to an occurrence of a context switchHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Mar 13, 2007·18 cites·22 claims
- 2471US5737757ACache tag system for use with multiple processors including the most recently requested processor identificationHEWLETT PACKARD CO·Filed 1997·Granted Apr 7, 1998·63 cites·4 claims
- 2569US6286095B1Computer apparatus having special instructions to force ordered load and store operationsHEWLETT PACKARD CO·Filed 1995·Granted Sep 4, 2001·61 cites·8 claims
- 2668US8879571B2Delays based on packet sizesZIEGLER MICHAEL L·Filed 2011·Granted Nov 4, 2014·2 cites·17 claims
- 2763US6651193B1Method for allowing distributed high performance coherent memory with full error containmentHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Nov 18, 2003·8 cites·6 claims
- 2861US4398243AData processing system having a unique instruction processor systemDATA GENERAL CORP·Filed 1980·Granted Aug 9, 1983·27 cites·17 claims
- 2960US8537859B2Reassembly of mini-packets in a bufferTRAUB STEVEN·Filed 2010·Granted Sep 17, 2013·3 cites·20 claims
- 3060US6880153B1Method and apparatus for varying the level of correctness checks executed when performing correctness checks opportunistically using spare instruction slotsHEWLETT PACKARD DEVELOPMENT CO·Filed 2000·Granted Apr 12, 2005·7 cites·16 claims
- 3155US6925535B2Program control flow conditioned on presence of requested data in cache memoryHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Aug 2, 2005·4 cites·9 claims
- 3255US4622630AData processing system having unique bus control protocolDATA GENERAL CORP·Filed 1983·Granted Nov 11, 1986·23 cites·13 claims
- 3353US6182176B1Queue-based predictive flow control mechanismHEWLETT PACKARD CO·Filed 1994·Granted Jan 30, 2001·22 cites·1 claims
- 3452US5515522ACoherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cacheHEWLETT PACKARD CO·Filed 1994·Granted May 7, 1996·25 cites·21 claims
- 3551US5528766AMultiple arbitration schemeHEWLETT PACKARD CO·Filed 1994·Granted Jun 18, 1996·22 cites·3 claims
- 3649US8046569B2Processing element having dual control stores to minimize branch latencyHEWLETT PACKARD DEVELOPMENT CO·Filed 2007·Granted Oct 25, 2011·0 cites·20 claims
- 3748US4493033ADual port cache with interleaved read accesses during alternate half-cycles and simultaneous writingDATA GENERAL CORP·Filed 1982·Granted Jan 8, 1985·15 cites·7 claims
- 3847US7478262B2Method for allowing distributed high performance coherent memory with full error containmentHEWLETT PACKARD DEVELOPMENT CO·Filed 2003·Granted Jan 13, 2009·0 cites·18 claims
- 3947US5519838AFast pipelined distributed arbitration schemeHEWLETT PACKARD CO·Filed 1994·Granted May 21, 1996·19 cites·6 claims
- 4047US2024058196A1Foot support system for a foot module of a rehabilitation mechanismReActive Robotics GmbH·Filed 2022·Application pending·0 cites
- 4146US8908711B2Target issue intervalsZIEGLER MICHAEL L·Filed 2011·Granted Dec 9, 2014·0 cites·16 claims
- 4246US8830838B2Node interface indicatorsZIEGLER MICHAEL L·Filed 2011·Granted Sep 9, 2014·0 cites·16 claims
- 4345US5784708ATranslation mechanism for input/output addressesHEWLETT PACKARD CO·Filed 1996·Granted Jul 21, 1998·19 cites·11 claims
- 4444US7346802B2Routing communications to a storage area networkHEWLETT PACKARD DEVELOPMENT CO·Filed 2004·Granted Mar 18, 2008·2 cites·20 claims
- 4544US2022245742A1Method and system for matching commercial properties and tenantsZIEGLER MICHAEL·Filed 2021·Application pending·0 cites
- 4643US8539113B2Indicators for streams associated with messagesZIEGLER MICHAEL L·Filed 2011·Granted Sep 17, 2013·0 cites·9 claims
- 4742US9172653B2Sending request messages to nodes indicated as unresolvedZIEGLER MICHAEL L·Filed 2011·Granted Oct 27, 2015·0 cites·15 claims
- 4840US2013223443A1Distribution trees with stagesZIEGLER MICHAEL L·Filed 2012·Application pending·0 cites
- 4939US2024074932A1Buttock support for at least partial load-relief of the body weight of a person, and load-relief system comprising such a buttock supportReActive Robotics GmbH·Filed 2022·Application pending·0 cites
- 5038US2012320909A1Sending request messages over designated communications channelsZIEGLER MICHAEL L·Filed 2011·Application pending·0 cites
Showing the top 50 of 51 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →