Inventor · disambiguated record
Sean Michael Carey
Also filed as: CAREY SEAN M · CAREY SEAN MICHAEL
11 granted patents·1 pending application·10 citations·filing 2007–2022
81Inventor score
Top patents by PatentIndex Score
12 records- 0183US11989071B2Dynamic guard band with timing protection and with performance protectionIBM·Filed 2022·Granted May 21, 2024·1 cites·20 claims
- 0267US11817697B2Method to limit the time a semiconductor device operates above a maximum operating voltageIBM·Filed 2022·Granted Nov 14, 2023·0 cites·25 claims
- 0364US7882472B2Method, apparatus, and computer program product for automatically waiving non-compute indications for a timing analysis processIBM·Filed 2007·Granted Feb 1, 2011·4 cites·20 claims
- 0459US7676779B2Logic block timing estimation using conesizeIBM·Filed 2007·Granted Mar 9, 2010·2 cites·16 claims
- 0556US8001411B2Generating a local clock domain using dynamic controlsIBM·Filed 2007·Granted Aug 16, 2011·3 cites·20 claims
- 0653US11953982B2Dynamic guard band with timing protection and with performance protectionIBM·Filed 2022·Granted Apr 9, 2024·0 cites·20 claims
- 0752US12282721B2Netlist design for post silicon local clock controller timing improvementIBM·Filed 2022·Granted Apr 22, 2025·0 cites·20 claims
- 0851US10215804B2Semiconductor power and performance optimizationIBM·Filed 2016·Granted Feb 26, 2019·0 cites·20 claims
- 0947US11501047B2Error injection for timing margin protection and frequency closureIBM·Filed 2019·Granted Nov 15, 2022·0 cites·20 claims
- 1042US10372851B2Independently projecting a canonical clockIBM·Filed 2017·Granted Aug 6, 2019·0 cites·17 claims
- 1142US2009070720A1System to Identify Timing Differences from Logic Block Changes and Associated MethodsIBM·Filed 2007·Application pending·0 cites
- 1235US8185371B2Modeling full and half cycle clock variabilityBHANJI ADIL·Filed 2009·Granted May 22, 2012·0 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →