Inventor · disambiguated record
Steven Lee Prins
Also filed as: PRINS STEVEN L · PRINS STEVEN LEE
10 granted patents·3 pending applications·4 citations·filing 2007–2022
80Inventor score
Top patents by PatentIndex Score
13 records- 0167US11251093B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2020·Granted Feb 15, 2022·0 cites·18 claims
- 0266US7790525B2Method of achieving dense-pitch interconnect patterning in integrated circuitsTEXAS INSTRUMENTS INC·Filed 2007·Granted Sep 7, 2010·2 cites·10 claims
- 0363US9117775B2Alignment to multiple layersATON THOMAS JOHN·Filed 2012·Granted Aug 25, 2015·1 cites·7 claims
- 0459US10734290B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2018·Granted Aug 4, 2020·0 cites·17 claims
- 0556US8216945B2Wafer planarity control between pattern levelsPRINS STEVEN L·Filed 2010·Granted Jul 10, 2012·1 cites·18 claims
- 0655US2024113156A1Thin film resistor mismatch improvement using a self-aligned double pattern (sadp) techniqueTEXAS INSTRUMENTS INC·Filed 2022·Application pending·0 cites
- 0754US10134643B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2017·Granted Nov 20, 2018·0 cites·11 claims
- 0854US9583488B2Poly gate extension design methodology to improve CMOS performance in dual stress liner process flowTEXAS INSTRUMENTS INC·Filed 2014·Granted Feb 28, 2017·0 cites·8 claims
- 0950US11522043B2IC with matched thin film resistorsTEXAS INSTRUMENTS INC·Filed 2020·Granted Dec 6, 2022·0 cites·22 claims
- 1050US9343332B2Alignment to multiple layersTEXAS INSTRUMENTS INC·Filed 2015·Granted May 17, 2016·0 cites·3 claims
- 1145US2009098702A1Method to Form CMOS Circuits Using Optimized SidewallsTEXAS INSTRUMENTS INC·Filed 2008·Application pending·0 cites
- 1244US2009096055A1Method to form cmos circuits with sub 50nm sti structures using selective epitaxial silicon post sti etchTEXAS INSTRUMENTS INC·Filed 2008·Application pending·0 cites
- 1339US8252609B2Curvature reduction for semiconductor wafersKIRKPATRICK BRIAN K·Filed 2010·Granted Aug 28, 2012·0 cites·21 claims
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