Inventor · disambiguated record
Anand Arunachalam
Also filed as: ARUNACHALAM ANAND
9 granted patents·115 citations·filing 2005–2016
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0192US7581197B2Relative positioning of circuit elements in circuit designSYNOPSYS INC·Filed 2005·Granted Aug 25, 2009·31 cites·35 claims
- 0290US7937682B2Method and apparatus for automatic orientation optimizationSYNOPSYS INC·Filed 2008·Granted May 3, 2011·26 cites·33 claims
- 0389US8984467B2Method and apparatus for automatic relative placement generation for clock treesARUNACHALAM ANAND·Filed 2011·Granted Mar 17, 2015·13 cites·27 claims
- 0488US9792396B2Method and apparatus for automatic relative placement generation for clock treesSYNOPSYS INC·Filed 2016·Granted Oct 17, 2017·5 cites·10 claims
- 0585US9430601B2Method and apparatus for automatic relative placement generation for clock treesSYNOPSYS INC·Filed 2015·Granted Aug 30, 2016·4 cites·24 claims
- 0683US9361417B2Placement of single-bit and multi-bit flip-flopsSYNOPSYS INC·Filed 2014·Granted Jun 7, 2016·12 cites·16 claims
- 0782US8239792B2Relative positioning of circuit elements in circuit designARUNACHALAM ANAND·Filed 2009·Granted Aug 7, 2012·10 cites·28 claims
- 0880US8434035B2Relative positioning of circuit elements in circuit designARUNACHALAM ANAND·Filed 2012·Granted Apr 30, 2013·5 cites·20 claims
- 0977US8751986B2Method and apparatus for automatic relative placement rule generationARUNACHALAM ANAND·Filed 2011·Granted Jun 10, 2014·9 cites·13 claims
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