Inventor · disambiguated record
Sreejit Chakravarty
Also filed as: CHAKRAVARTY SREEJIT
23 granted patents·6 pending applications·117 citations·filing 1999–2023
94Inventor score
Top patents by PatentIndex Score
29 records- 0192US9256505B2Data transformations to improve ROM yield and programming timeLSI CORP·Filed 2014·Granted Feb 9, 2016·17 cites·20 claims
- 0290US8583973B1Stored-pattern logic self-testing with serial communicationLSI CORP·Filed 2013·Granted Nov 12, 2013·9 cites·6 claims
- 0385US8473792B2Logic BIST for system testing using stored patternsCHAKRAVARTY SREEJIT·Filed 2011·Granted Jun 25, 2013·6 cites·19 claims
- 0480US10491381B2In-field system test securityINTEL CORP·Filed 2017·Granted Nov 26, 2019·2 cites·25 claims
- 0579US11335428B2Methods, systems and apparatus for in-field testing for generic diagnostic componentsINTEL CORP·Filed 2018·Granted May 17, 2022·6 cites·25 claims
- 0678US7971169B1System and method for reducing the generation of inconsequential violations resulting from timing analysesLSI CORP·Filed 2008·Granted Jun 28, 2011·10 cites·20 claims
- 0777US8090965B1System and method for testing memory power management modes in an integrated circuitCHAKRAVARTY SREEJIT·Filed 2008·Granted Jan 3, 2012·8 cites·23 claims
- 0877US8010935B2Electronic design automation tool and method for optimizing the placement of process monitors in an integrated circuitLSI CORP·Filed 2008·Granted Aug 30, 2011·4 cites·20 claims
- 0975US6598211B2Scaleable approach to extracting bridges from a hierarchically described VLSI layoutINTEL CORP·Filed 2001·Granted Jul 22, 2003·28 cites·25 claims
- 1071US8711645B2Victim port-based design for test area overhead reduction in multiport latch-based memoriesCHAKRAVARTY SREEJIT·Filed 2012·Granted Apr 29, 2014·4 cites·16 claims
- 1171US8191029B2Timing error sampling generator, critical path monitor for hold and setup violations of an integrated circuit and a method of timing testingTETELBAUM ALEXANDER·Filed 2008·Granted May 29, 2012·4 cites·16 claims
- 1269US8464198B1Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuitCHAKRAVARTY SREEJIT·Filed 2008·Granted Jun 11, 2013·4 cites·20 claims
- 1369US7802159B1Enhanced logic built-in self-test module and method of online system testing employing the sameLSI CORP·Filed 2008·Granted Sep 21, 2010·5 cites·20 claims
- 1465US8228750B2Low cost comparator design for memory BISTCHAKRAVARTY SREEJIT·Filed 2010·Granted Jul 24, 2012·3 cites·20 claims
- 1564US8499230B2Critical path monitor for an integrated circuit and method of operation thereofCHAKRAVARTY SREEJIT·Filed 2008·Granted Jul 30, 2013·1 cites·20 claims
- 1662US11257560B2Test architecture for die to die interconnect for three dimensional integrated circuitsINTEL CORP·Filed 2017·Granted Feb 22, 2022·1 cites·9 claims
- 1761US8656233B2Scan cell designs with serial and parallel loading of test dataCHAKRAVARTY SREEJIT·Filed 2010·Granted Feb 18, 2014·1 cites·13 claims
- 1860US8418008B2Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuitCHAKRAVARTY SREEJIT·Filed 2008·Granted Apr 9, 2013·4 cites·22 claims
- 1954US2025068529A1Test and repair architecture for inter and intra cluster defectsINTEL CORP·Filed 2023·Application pending·0 cites
- 2051US8473890B2Timing error sampling generator and a method of timing testingTETELBAUM ALEXANDER·Filed 2012·Granted Jun 25, 2013·0 cites·14 claims
- 2148US2024027516A1Test and repair of interconnects between chipsCHAKRAVARTY SREEJIT·Filed 2022·Application pending·0 cites
- 2246US10859627B2In-field system testingINTEL CORP·Filed 2017·Granted Dec 8, 2020·0 cites·25 claims
- 2343US2023084463A1Runtime non-destructive memory built-in self-test (bist)INTEL CORP·Filed 2022·Application pending·0 cites
- 2438US8793549B2Low-cost design for register file testabilityCHAKRAVARTY SREEJIT·Filed 2010·Granted Jul 29, 2014·0 cites·20 claims
- 2538US2012173938A1Scan cell designs with serial and parallel loading of test dataCHAKRAVARTY SREEJIT·Filed 2010·Application pending·0 cites
- 2637US2015262710A1Method and system for reducing memory test time utilizing a built-in self-test architectureLSI CORP·Filed 2014·Application pending·0 cites
- 2736US2013111285A1Scan test circuitry comprising scan cells with functional output multiplexingCHAKRAVARTY SREEJIT·Filed 2011·Application pending·0 cites
- 2825US6519499B1Method and apparatus for extracting bridges from an integrated circuit layoutINTEL CORP·Filed 1999·Granted Feb 11, 2003·0 cites·26 claims
- 2925US6502004B1Method and apparatus for extracting bridges from an integrated circuit layoutINTEL CORP·Filed 1999·Granted Dec 31, 2002·0 cites·28 claims
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