Inventor · disambiguated record
Mark Birman
Also filed as: BIRMAN MARK
19 granted patents·2 pending applications·388 citations·filing 1988–2025
95Inventor score
Files withNETLOGIC MICROSYSTEMS INC11AVAGO TECH INT SALES PTE LID4WEITEK CORP2BIRMAN MARK1BROADCOM CORP1
Top patents by PatentIndex Score
21 records- 0198US7660140B1Content addresable memory having selectively interconnected counter circuitsNETLOGIC MICROSYSTEMS INC·Filed 2008·Granted Feb 9, 2010·59 cites·24 claims
- 0298US7643353B1Content addressable memory having programmable interconnect structureNETLOGIC MICROSYSTEMS INC·Filed 2008·Granted Jan 5, 2010·69 cites·32 claims
- 0396US7881125B2Power reduction in a content addressable memory having programmable interconnect structureNETLOGIC MICROSYSTEMS INC·Filed 2010·Granted Feb 1, 2011·19 cites·12 claims
- 0495US7916510B1Reformulating regular expressions into architecture-dependent bit groupsNETLOGIC MICROSYSTEMS INC·Filed 2010·Granted Mar 29, 2011·32 cites·30 claims
- 0594US7876590B2Content addressable memory having selectively interconnected rows of counter circuitsNETLOGIC MICROSYSTEMS INC·Filed 2010·Granted Jan 25, 2011·14 cites·9 claims
- 0693US7924590B1Compiling regular expressions for programmable content addressable memory devicesNETLOGIC MICROSYSTEMS INC·Filed 2010·Granted Apr 12, 2011·19 cites·30 claims
- 0793US7787275B1Content addressable memory having programmable combinational logic circuitsNETLOGIC MICROSYSTEMS INC·Filed 2008·Granted Aug 31, 2010·19 cites·28 claims
- 0892US7826242B2Content addresable memory having selectively interconnected counter circuitsNETLOGIC MICROSYSTEMS INC·Filed 2009·Granted Nov 2, 2010·16 cites·27 claims
- 0989US7821844B2Content addresable memory having programmable interconnect structureNETLOGIC MICROSYSTEMS INC·Filed 2009·Granted Oct 26, 2010·12 cites·15 claims
- 1084US8812480B1Targeted search system with de-obfuscating functionalityWATSON GREG·Filed 2012·Granted Aug 19, 2014·10 cites·40 claims
- 1172US8214305B1Pattern matching system and method for data streams, including deep packet inspectionBIRMAN MARK·Filed 2008·Granted Jul 3, 2012·8 cites·24 claims
- 1268US5021985AVariable latency method and apparatus for floating-point coprocessorWEITEK CORP·Filed 1990·Granted Jun 4, 1991·58 cites·12 claims
- 1367US2024414208A1High performance architecture for converged security systems and appliancesAVAGO TECH INT SALES PTE LID·Filed 2024·Application pending·0 cites
- 1465US2025181520A1Circuitry with address scramblingAVAGO TECH INT SALES PTE LID·Filed 2025·Application pending·0 cites
- 1564US7836246B2Method and apparatus for overlaying flat and/or tree based data sets onto content addressable memory (CAM) deviceNETLOGIC MICROSYSTEMS INC·Filed 2008·Granted Nov 16, 2010·6 cites·19 claims
- 1663US12259827B2Systems and methods for address scramblingAVAGO TECH INT SALES PTE LID·Filed 2023·Granted Mar 25, 2025·0 cites·18 claims
- 1763US4901267AFloating point circuit with configurable number of multiplier cycles and variable divide cycle ratioWEITEK CORP·Filed 1988·Granted Feb 13, 1990·35 cites·7 claims
- 1861US12101356B2High performance architecture for converged security systems and appliancesAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Sep 24, 2024·0 cites·15 claims
- 1957US7461200B1Method and apparatus for overlaying flat and tree based data sets onto content addressable memory (CAM) deviceNETLOGIC MICROSYSTEMS INC·Filed 2004·Granted Dec 2, 2008·11 cites·23 claims
- 2054US8631195B1Content addressable memory having selectively interconnected shift register circuitsKHANNA SANDEEP·Filed 2008·Granted Jan 14, 2014·1 cites·20 claims
- 2140US9269411B2Organizing data in a hybrid memory for search operationsBROADCOM CORP·Filed 2012·Granted Feb 23, 2016·0 cites·20 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →