Inventor · disambiguated record
David A. Hrusecky
Also filed as: HRUSECKY DAVID A · HRUSECKY DAVID ALLEN
63 granted patents·7 pending applications·759 citations·filing 1986–2024
99Inventor score
Top patents by PatentIndex Score
70 records- 0196US10037211B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2016·Granted Jul 31, 2018·15 cites·17 claims
- 0292US11755324B2Gather buffer management for unaligned and gather load operationsIBM·Filed 2021·Granted Sep 12, 2023·2 cites·19 claims
- 0391US10042647B2Managing a divided load reorder queueIBM·Filed 2016·Granted Aug 7, 2018·6 cites·20 claims
- 0491US10042770B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Aug 7, 2018·6 cites·7 claims
- 0591US10037229B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2016·Granted Jul 31, 2018·6 cites·13 claims
- 0691US9983875B2Operation of a multi-slice processor preventing early dependent instruction wakeupIBM·Filed 2016·Granted May 29, 2018·9 cites·17 claims
- 0791US9934033B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 3, 2018·8 cites·11 claims
- 0889US9940133B2Operation of a multi-slice processor implementing simultaneous two-target loads and storesIBM·Filed 2016·Granted Apr 10, 2018·6 cites·6 claims
- 0986US7809924B2System for generating effective addressIBM·Filed 2008·Granted Oct 5, 2010·15 cites·5 claims
- 1086US7729421B2Low latency video decoder with high-quality, variable scaling and minimal frame buffer memoryIBM·Filed 2002·Granted Jun 1, 2010·33 cites·9 claims
- 1186US7318127B2Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processorIBM·Filed 2005·Granted Jan 8, 2008·17 cites·14 claims
- 1286US6898327B1Anti-flicker system for multi-plane graphicsIBM·Filed 2000·Granted May 24, 2005·32 cites·23 claims
- 1385US7050113B2Digital video data scaler and methodIBM·Filed 2002·Granted May 23, 2006·29 cites·24 claims
- 1485US6996174B2MPEG video decoder with integrated scaling and display functionsIBM·Filed 2002·Granted Feb 7, 2006·25 cites·2 claims
- 1584US7284094B2Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence classIBM·Filed 2005·Granted Oct 16, 2007·14 cites·18 claims
- 1683US9798549B1Out-of-order processor that avoids deadlock in processing queues by designating a most favored instructionIBM·Filed 2016·Granted Oct 24, 2017·3 cites·13 claims
- 1782US11061810B2Virtual cache mechanism for program break point register exception handlingIBM·Filed 2019·Granted Jul 13, 2021·3 cites·18 claims
- 1882US10073697B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2016·Granted Sep 11, 2018·2 cites·5 claims
- 1982US6470051B1MPEG video decoder with integrated scaling and display functionsIBM·Filed 1999·Granted Oct 22, 2002·63 cites·46 claims
- 2081US10133576B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2015·Granted Nov 20, 2018·2 cites·18 claims
- 2181US6317164B1System for creating multiple scaled videos from encoded video sourcesIBM·Filed 1999·Granted Nov 13, 2001·68 cites·15 claims
- 2280US12061909B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2023·Granted Aug 13, 2024·0 cites·21 claims
- 2379US10409598B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Sep 10, 2019·1 cites·5 claims
- 2479US6442206B1Anti-flicker logic for MPEG video decoder with integrated scaling and display functionsIBM·Filed 1999·Granted Aug 27, 2002·58 cites·29 claims
- 2578US5973740AMulti-format reduced memory video decoder with adjustable polyphase expansion filterIBM·Filed 1998·Granted Oct 26, 1999·58 cites·29 claims
- 2675US5777679AVideo decoder including polyphase fir horizontal filterIBM·Filed 1996·Granted Jul 7, 1998·50 cites·4 claims
- 2774US11734010B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2021·Granted Aug 22, 2023·0 cites·21 claims
- 2874US10564978B2Operation of a multi-slice processor with an expanded merge fetching queueIBM·Filed 2018·Granted Feb 18, 2020·1 cites·14 claims
- 2974US10067763B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2015·Granted Sep 4, 2018·1 cites·9 claims
- 3074US6642934B2Color mapped and direct color OSD region processor with support for 4:2:2 profile decode functionIBM·Filed 2002·Granted Nov 4, 2003·10 cites·32 claims
- 3173US8086801B2Loading data to vector renamed register from across multiple cache linesHRUSECKY DAVID A·Filed 2009·Granted Dec 27, 2011·8 cites·20 claims
- 3273US7360058B2System and method for generating effective addressIBM·Filed 2005·Granted Apr 15, 2008·6 cites·3 claims
- 3373US6542162B1Color mapped and direct color OSD region processor with support for 4:2:2 profile decode functionIBM·Filed 1998·Granted Apr 1, 2003·34 cites·14 claims
- 3473US6529244B1Digital video decode system with OSD processor for converting graphics data in 4:4:4 format to 4:2:2 format by mathematically combining chrominance valuesIBM·Filed 1999·Granted Mar 4, 2003·43 cites·9 claims
- 3570US12411688B2Gather buffer management for unaligned and gather load operationsIBM·Filed 2023·Granted Sep 9, 2025·0 cites·18 claims
- 3668US10884742B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Jan 5, 2021·0 cites·9 claims
- 3768US8422313B2Reduced power consumption memory circuitryBUETTNER STEFAN·Filed 2011·Granted Apr 16, 2013·4 cites·20 claims
- 3868US5929911AMultiformat reduced memory MPEG-2 compliant decoderIBM·Filed 1997·Granted Jul 27, 1999·33 cites·42 claims
- 3967US10831481B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2019·Granted Nov 10, 2020·0 cites·14 claims
- 4067US10423423B2Efficiently managing speculative finish tracking and error handling for load instructionsIBM·Filed 2015·Granted Sep 24, 2019·1 cites·13 claims
- 4167US6999105B2Image scaling employing horizontal partitioningIBM·Filed 2003·Granted Feb 14, 2006·14 cites·23 claims
- 4264US11150907B2Parallel slice processor having a recirculating load-store queue for fast deallocation of issue queue entriesIBM·Filed 2018·Granted Oct 19, 2021·0 cites·19 claims
- 4364US10496406B2Handling unaligned load operations in a multi-slice computer processorIBM·Filed 2018·Granted Dec 3, 2019·0 cites·9 claims
- 4463US10268518B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 23, 2019·0 cites·13 claims
- 4563US10255107B2Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructionsIBM·Filed 2018·Granted Apr 9, 2019·0 cites·7 claims
- 4663US5375078AArithmetic unit for performing XY+B operationIBM·Filed 1992·Granted Dec 20, 1994·39 cites·21 claims
- 4759US11321088B2Tracking load and store instructions and addresses in an out-of-order processorIBM·Filed 2020·Granted May 3, 2022·0 cites·25 claims
- 4858US11314510B2Tracking load and store instructions and addresses in an out-of-order processorIBM·Filed 2020·Granted Apr 26, 2022·0 cites·25 claims
- 4957US9495297B2Cache line crossing load techniques for a caching systemIBM·Filed 2014·Granted Nov 15, 2016·0 cites·11 claims
- 5057US2025335198A1Low power late-selected caches using a set-prediction historyIBM·Filed 2024·Application pending·0 cites
Showing the top 50 of 70 patent records by PatentIndex Score.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →